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Merge branch 'h7' into befree2008-h7
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@Nightwalker-87
Nightwalker-87 committed Sep 20, 2020
2 parents 9c396f8 + 9950f14 commit 72df399
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Showing 6 changed files with 705 additions and 468 deletions.
9 changes: 8 additions & 1 deletion inc/stlink.h
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,11 @@ enum target_state {

#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43

//add by wliang
#define STLINK_DEBUG_APIV2_READ_DAP_REG 0x45
#define STLINK_DEBUG_APIV2_WRITE_DAP_REG 0x46
//add by wliang

#define STLINK_APIV3_SET_COM_FREQ 0x61
#define STLINK_APIV3_GET_COM_FREQ 0x62

Expand Down Expand Up @@ -126,7 +131,9 @@ enum stlink_flash_type {
STLINK_FLASH_TYPE_L4, // l4, l4+ */
STLINK_FLASH_TYPE_G0,
STLINK_FLASH_TYPE_G4,
STLINK_FLASH_TYPE_WB
STLINK_FLASH_TYPE_WB,
//add by wliang
STLINK_FLASH_TYPE_H7
};

struct stlink_reg {
Expand Down
129 changes: 116 additions & 13 deletions src/common.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -286,7 +286,26 @@
#define FLASH_F4_CR_SNB_MASK 0xf8
#define FLASH_F4_SR_BSY 16

// STM32F2
//STM32H7xx
#define FLASH_H7_CR_LOCK 0
#define FLASH_H7_CR_PG 1
#define FLASH_H7_CR_BER 3
#define FLASH_H7_CR_PSIZE 4
#define FLASH_H7_CR_START 7
#define FLASH_H7_CR_SNB 8

#define FLASH_H7_SR_BSY 0
#define FLASH_H7_SR_QW 2

#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000)
#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04)
#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0C)
#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10)




//STM32F2
#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00)
#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04)
#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08)
Expand Down Expand Up @@ -367,7 +386,8 @@ static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
return(rdp & 0xff);
}

static inline uint32_t read_flash_cr(stlink_t *sl) {
//inline
static uint32_t read_flash_cr(stlink_t *sl) {
uint32_t reg, res;

if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
Expand All @@ -376,6 +396,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) {
reg = FLASH_F7_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
reg = STM32L4_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
reg = FLASH_H7_CR1;
} else if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
reg = STM32Gx_FLASH_CR;
Expand Down Expand Up @@ -431,6 +453,9 @@ static inline unsigned int is_flash_locked(stlink_t *sl) {
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
cr_lock_shift = STM32WB_FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = FLASH_H7_CR1;
cr_lock_shift = FLASH_H7_CR_LOCK;
} else {
ELOG("unsupported flash method, abort\n");
return(-1);
Expand Down Expand Up @@ -467,6 +492,8 @@ static void unlock_flash(stlink_t *sl) {
key_reg = STM32Gx_FLASH_KEYR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
key_reg = STM32WB_FLASH_KEYR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
key_reg = FLASH_H7_KEYR1;
} else {
ELOG("unsupported flash method, abort\n");
return;
Expand Down Expand Up @@ -522,6 +549,9 @@ static void lock_flash(stlink_t *sl) {
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
cr_lock_shift = STM32WB_FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = FLASH_H7_CR1;
cr_lock_shift = FLASH_H7_CR_LOCK;
} else {
ELOG("unsupported flash method, abort\n");
return;
Expand Down Expand Up @@ -724,6 +754,9 @@ static void set_flash_cr_pg(stlink_t *sl) {
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
x |= (1 << FLASH_CR_PG);
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = FLASH_H7_CR1;
x |= (1 << FLASH_H7_CR_PG);
} else {
cr_reg = FLASH_CR;
x = (1 << FLASH_CR_PG);
Expand Down Expand Up @@ -901,7 +934,10 @@ static void set_flash_cr_strt(stlink_t *sl) {
cr_strt = (1 << STM32Gx_FLASH_CR_STRT);
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
cr_strt = (1 << STM32WB_FLASH_CR_STRT);
cr_strt = 1 << STM32WB_FLASH_CR_STRT;
}else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = FLASH_H7_CR1;
cr_strt = 1 << FLASH_H7_CR_START;
} else {
cr_reg = FLASH_CR;
cr_strt = (1 << FLASH_CR_STRT);
Expand Down Expand Up @@ -939,6 +975,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) {
sr_reg = STM32Gx_FLASH_SR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
sr_reg = STM32WB_FLASH_SR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
sr_reg = FLASH_H7_SR1;
} else {
ELOG("unsupported flash method, abort");
return(-1);
Expand Down Expand Up @@ -973,6 +1011,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) {
sr_busy_shift = STM32Gx_FLASH_SR_BSY;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
sr_busy_shift = STM32WB_FLASH_SR_BSY;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
sr_busy_shift = FLASH_SR_BSY;
} else {
ELOG("unsupported flash method, abort");
return(-1);
Expand All @@ -993,6 +1033,23 @@ static void wait_flash_busy(stlink_t *sl) {
;
}

// STM32H7 need check QW flag
static inline unsigned int is_queuewait_flag(stlink_t *sl) {
uint32_t sr_waitflag_shift;
unsigned int res;

sr_waitflag_shift = FLASH_H7_SR_QW;
res = read_flash_sr(sl) & (1 << sr_waitflag_shift);

return res;
}

static void wait_QW_busy(stlink_t *sl) {
/* todo: add some delays here */
while (is_queuewait_flag(sl))
;
}

static void wait_flash_busy_progress(stlink_t *sl) {
int i = 0;
fprintf(stdout, "Mass erasing");
Expand Down Expand Up @@ -1065,8 +1122,13 @@ static inline void write_flash_ar2(stlink_t *sl, uint32_t n) {

static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
uint32_t x = read_flash_cr(sl);
x &= ~(0x03 << 8);
x |= (n << 8);
//stm32h7 support
if (sl->flash_type == STLINK_FLASH_TYPE_H7){
x &= ~(0x03 << FLASH_H7_CR_PSIZE);
x |= (n << FLASH_H7_CR_PSIZE);
stlink_write_debug32(sl, FLASH_H7_CR1, x);
return ;
}
#if DEBUG_FLASH
fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
#endif
Expand All @@ -1085,6 +1147,17 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
stlink_write_debug32(sl, FLASH_F4_CR, x);
}

//stm32h7 choose right bank number and sector number
static inline void write_flash_cr_ber_snb(stlink_t *sl, uint32_t n) {
uint32_t x = read_flash_cr(sl);
x |= (n << FLASH_H7_CR_SNB);
x |= (1 << FLASH_H7_CR_BER);
#if DEBUG_FLASH
fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
#endif
stlink_write_debug32(sl, FLASH_H7_CR1, x);
}

static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY));
uint32_t x = read_flash_cr(sl);
Expand Down Expand Up @@ -1162,16 +1235,22 @@ int stlink_core_id(stlink_t *sl) {
}

// stlink_chip_id() is called by stlink_load_device_params()
// do not call this procedure directly.
// Do not call this procedure directly.
int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
int ret;

ret = stlink_read_debug32(sl, 0xE0042000, chip_id);

if (ret == -1) {
return(ret);
if (ret == -1) { return ret; }

// STM32H7 chipid in 0x5C001000
if (*chip_id == 0) {
ret = stlink_read_debug32(sl, 0x5C001000, chip_id);
if (ret == -1) { return ret; }
}

if (ret == -1) { return(ret); }

if (*chip_id == 0) {
// Try Corex M0 DBGMCU_IDCODE register address
ret = stlink_read_debug32(sl, 0x40015800, chip_id);
Expand Down Expand Up @@ -1660,8 +1739,7 @@ void stlink_print_data(stlink_t * sl) {
}
*/
}
//DLOG(" %02x", (unsigned int) sl->q_buf[i]);
fprintf(stderr, " %02x", (unsigned int) sl->q_buf[i]);
DLOG(" %02x\n", (unsigned int) sl->q_buf[i]);
}
//DLOG("\n\n");
fprintf(stderr, "\n");
Expand Down Expand Up @@ -2135,6 +2213,11 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) {
}

}
//add by wliang
uint32_t calculate_H7_sectornum(uint32_t flashaddr){
flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
return(flashaddr/0x20000);
}

// returns BKER:PNB for the given page address
uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
Expand Down Expand Up @@ -2209,6 +2292,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) {
int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
if (sl->flash_type == STLINK_FLASH_TYPE_F4 ||
sl->flash_type == STLINK_FLASH_TYPE_F7 ||
sl->flash_type == STLINK_FLASH_TYPE_H7 ||
sl->flash_type == STLINK_FLASH_TYPE_L4) {
// wait for ongoing op to finish
wait_flash_busy(sl);
Expand Down Expand Up @@ -2237,6 +2321,15 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ",
sector, stlink_calculate_pagesize(sl, flashaddr));
write_flash_cr_snb(sl, sector);
} else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) {

// add by wliang
uint32_t sector=calculate_H7_sectornum(flashaddr);

fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr));

write_flash_cr_ber_snb(sl, sector);

} else {
// calculate the actual page from the address
uint32_t sector = calculate_F4_sectornum(flashaddr);
Expand Down Expand Up @@ -2613,6 +2706,7 @@ int stlink_write_flash(

if ((sl->flash_type == STLINK_FLASH_TYPE_F4) ||
(sl->flash_type == STLINK_FLASH_TYPE_F7) ||
(sl->flash_type == STLINK_FLASH_TYPE_H7) ||
(sl->flash_type == STLINK_FLASH_TYPE_L4)) {
// TODO: check write operation

Expand Down Expand Up @@ -2674,9 +2768,18 @@ int stlink_write_flash(
size_t size = len - off > buf_size ? buf_size : len - off;
printf("size: %u\n", (unsigned int)size);

if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) {
ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off);
return(-1);
// STM32H7 program flash directly
if (sl->flash_type == STLINK_FLASH_TYPE_H7){
size = 32;
wait_QW_busy(sl);
memcpy(sl->q_buf, base + off, size);
stlink_write_mem32(sl, addr + (uint32_t) off, size);
wait_QW_busy(sl);
} else {
if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) {
ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off);
return -1;
}
}

off += size;
Expand Down
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