The MTIP bit in mip register is read-only

[SKTT1Ryze]

In the riscv-privileged manual, it is said that "The MTIP bit (in mip) is read-only and is cleared by writing to the memory-mapped machine-mode timer compare register."
But in the riscv crate, there is an interface like this:

use riscv::register::mip;
use riscv_rt::entry;

#[entry]  
fn main() {
    mip::set_mtimer();
}

We can write the code mip::set_mtimer() to set the 7th bit, the MTIP bit, of the mip register, which does not permitted in riscv-privileged manual.
Is there some reason for the existence of mip::set_mtimer()? If not, I suggest remove it.
Thanks.

[luojia65]

This should be a mistake, we should check and delete them in future releases.