Externalize icache / read-only cache dependency

.gitmodules

@@ -43,3 +43,6 @@
 [submodule "hardware/deps/dram_rtl_sim"]
 	path = hardware/deps/dram_rtl_sim
 	url = https://github.com/pulp-platform/dram_rtl_sim.git
+[submodule "hardware/deps/cluster_icache"]
+	path = hardware/deps/cluster_icache
+	url = https://github.com/pulp-platform/cluster_icache.git

Bender.lock

@@ -15,6 +15,16 @@ packages:
     - common_cells
     - common_verification
     - tech_cells_generic
+  cluster_icache:
+    revision: 0e1fb6751d9684d968ba7fb40836e6118b448ecd
+    version: 0.1.1
+    source:
+      Git: https://github.com/pulp-platform/cluster_icache.git
+    dependencies:
+    - axi
+    - common_cells
+    - scm
+    - tech_cells_generic
   cluster_interconnect:
     revision: null
     version: null
@@ -79,6 +89,12 @@ packages:
     dependencies:
     - axi
     - common_cells
+  scm:
+    revision: null
+    version: null
+    source:
+      Path: hardware/deps/scm
+    dependencies: []
   snitch:
     revision: null
     version: null

Bender.yml

@@ -15,6 +15,7 @@ dependencies:
   snitch:               { path: "hardware/deps/snitch"                                                       }
   tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git",   version: 0.2.13  }
   fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: pulp-v0.1.3 }
+  cluster_icache:       { git: "https://github.com/pulp-platform/cluster_icache.git",       version: 0.1.1   }
 
 workspace:
   checkout_dir: "./hardware/deps"
@@ -34,7 +35,6 @@ sources:
   - hardware/src/address_scrambler.sv
   - hardware/src/axi2mem.sv
   - hardware/src/bootrom.sv
-  - hardware/src/latch_scm.sv
   # Level 1
   - hardware/src/mempool_tile.sv
   # Level 2

CHANGELOG.md

@@ -33,6 +33,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Update `common_verification` to 0.2.3
 - Update `register_interface` to 0.4.3
 - Updated Halide to version 15
+- Move instruction cache into its own dependency
 
 ### Fixed
 - Fix type issue in `snitch_addr_demux`

Makefile

@@ -173,6 +173,7 @@ clean-dram:
 	fi
 
 build-dram: clean-dram
+	git submodule update --init --recursive -- $(DRAM_PATH)
 	if [ ! -d "$(DRAMSYS_PATH)" ]; then \
 		git clone https://github.com/tukl-msd/DRAMSys.git $(DRAMSYS_PATH); \
 	fi
@@ -190,7 +191,7 @@ setup-dram: config-dram
 	cd $(DRAMSYS_PATH) && \
 	if [ ! -d "build" ]; then \
 		mkdir build && cd build; \
-		cmake -DCMAKE_CXX_FLAGS=-fPIC -DCMAKE_C_FLAGS=-fPIC -D DRAMSYS_WITH_DRAMPOWER=ON .. ; \
+		$(CMAKE) -DCMAKE_CXX_FLAGS=-fPIC -DCMAKE_C_FLAGS=-fPIC -D DRAMSYS_WITH_DRAMPOWER=ON .. ; \
 		make -j; \
 	fi
 

hardware/deps/scm/Bender.yml

@@ -0,0 +1,8 @@
+package:
+  name: scm
+
+sources:
+  - defines:
+      TARGET_SCM_USE_LATCH_SCM: 1
+    files:
+      - latch_scm/register_file_1r_1w.sv

hardware/src/latch_scm.sv → hardware/deps/scm/latch_scm/register_file_1r_1w.sv

@@ -1,8 +1,39 @@
-// Copyright 2021 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-
-module latch_scm #(
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+////////////////////////////////////////////////////////////////////////////////
+// Company:        Institute of Integrated Systems // ETH Zurich              //
+//                                                                            //
+// Engineer:      Igor Loi - igor.loi@unibo.it                                //
+//                                                                            //
+// Additional contributions by:                                               //
+//                 Francesco Conti                                            //
+//                 Davide Rossi                                               //
+//                 Michael Gautschi                                           //
+//                 Antonio Pullini                                            //
+//                                                                            //
+// Create Date:    12/03/2015                                                 //
+// Design Name:    scm memory                                                 //
+// Module Name:    register_file_1r_1w                                        //
+// Project Name:   HWCE                                                       //
+// Language:       SystemVerilog                                              //
+//                                                                            //
+// Description:    scm memory multiport: FOR HWCE                             //
+//                                                                            //
+// Revision:                                                                  //
+// Revision v0.1 - File Created                                               //
+// Revision v0.2 - Improved Identation                                        //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+module register_file_1r_1w #(
   parameter ADDR_WIDTH    = 5,
   parameter DATA_WIDTH    = 32
 ) (

hardware/deps/snitch/Bender.yml

@@ -19,7 +19,6 @@ sources:
     - src/riscv_instr.sv
     - src/snitch_pkg.sv
     - src/snitch_axi_pkg.sv
-    - src/snitch_icache/snitch_icache_pkg.sv
     # rest of RTL
     - src/snitch.sv
     - src/snitch_regfile_ff.sv
@@ -32,12 +31,3 @@ sources:
     - src/snitch_shared_muldiv.sv
     - src/snitch_demux.sv
     - src/snitch_axi_adapter.sv
-    - src/snitch_icache/snitch_icache.sv
-    - src/snitch_icache/snitch_icache_l0.sv
-    - src/snitch_icache/snitch_icache_handler.sv
-    - src/snitch_icache/snitch_icache_lfsr.sv
-    - src/snitch_icache/snitch_icache_lookup_parallel.sv
-    - src/snitch_icache/snitch_icache_lookup_serial.sv
-    - src/snitch_icache/snitch_icache_refill.sv
-    - src/snitch_read_only_cache/snitch_axi_to_cache.sv
-    - src/snitch_read_only_cache/snitch_read_only_cache.sv