Merge pull request #350 from hansfbaier/master

Add W9812G6JB SDRAM module
enjoy-digital · Nov 9, 2023 · e1434fa · e1434fa
2 parents 4dec115 + 9cffe39
commit e1434fa
Showing 1 changed file with 9 additions and 0 deletions.
diff --git a/litedram/modules.py b/litedram/modules.py
@@ -553,6 +553,15 @@ class W9825G6KH6(SDRModule):
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 60), tFAW=None, tRAS=42)}
 
+class W9812G6JB(SDRModule):
+    # geometry
+    nbanks = 4
+    nrows  = 4096
+    ncols  = 512
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 12))
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=20, tRFC=(None, 60), tFAW=None, tRAS=42)}
+
 # DDR ----------------------------------------------------------------------------------------------
 
 class DDRModule(SDRAMModule):                     memtype = "DDR"