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#214 opened Aug 3, 2020 by enjoy-digital
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49 Open 114 Closed
49 Open 114 Closed
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Issues list

Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO bug?
#358 opened May 6, 2024 by epsilon537
2
Adding support to gowin phys in litedram.gen? enhancement
#357 opened Apr 28, 2024 by linhz0hz
1
LiteDRAMDMAWriter sinks data when not enabled bug?
#356 opened Apr 24, 2024 by DaveBerkeley
2
Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file, bug?
#355 opened Mar 30, 2024 by fontamsoc
GENDDRPHY support?
#353 opened Jan 20, 2024 by rhgndf
litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)
#349 opened Oct 5, 2023 by jersey99
5
DE10-Lite Memory initialization failed
#347 opened Sep 6, 2023 by LearnShareAlways
Underclocking DRAM controler to increase access time
#346 opened Aug 27, 2023 by denishoornaert
LiteDRAM core targeting DDR3 issues activate command twice for a write operation
#345 opened Aug 17, 2023 by dinaabdelbaky
LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.
#344 opened Aug 17, 2023 by dinaabdelbaky
1
Axi port write data error
#342 opened Jun 7, 2023 by Yuxin-Yu
8
Is it possible to adjust burst-length in order to widen data path ?
#339 opened May 22, 2023 by fontamsoc
wb_ctrl ports of ECP5 litedram_core generated for OrangeCrab02-25F failing when user_ports is native
#338 opened May 8, 2023 by fontamsoc
LiteDRAMDMAWriter cannot write accurate data to a specific address?
#336 opened Apr 25, 2023 by Prigana
AxSIZE mismatch?
#334 opened Apr 24, 2023 by TheZoq2
1
1
Setting for user_clk question
#333 opened Apr 23, 2023 by ztachip
1
ulx3s example does not work add-answer-to-wiki
#329 opened Apr 1, 2023 by TheZoq2
3
DDR4 reads without DQS at high speeds? question
#328 opened Feb 28, 2023 by alexey-morozov
1
Carrying out the LiteDRAM standalone core initialization manually, through wishbone ctrl interface
#327 opened Feb 28, 2023 by dinaabdelbaky
5
--top-module 'sim' was not found in the design question
#325 opened Jan 28, 2023 by CarrolXC
5
Corresponding verilog testbench for ASIC question
#317 opened Jan 4, 2023 by CarrolXC
1
submodules verilog question
#316 opened Dec 26, 2022 by CarrolXC
2
sdram_init() vs. init_sequence()
#315 opened Dec 23, 2022 by epsilon537
Typical litedram-L2 port sizes
#312 opened Oct 29, 2022 by bala122
QuarterRateGENSDRPHY
#308 opened Jun 25, 2022 by machdyne
2
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