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Merged
merged 4 commits into from
Jul 8, 2025
Merged

Fix remaining aarch64 clippy issues #1849

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0f39450
fix whitespace in `aarch64.spec.yml`
folkertdev Jul 8, 2025
1c3b0eb
remote intermediate assignment
folkertdev Jul 8, 2025
9a41bdb
shorten array literals
folkertdev Jul 8, 2025
ed6e3f9
remove unneeded cast
folkertdev Jul 8, 2025
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44 changes: 10 additions & 34 deletions crates/core_arch/src/aarch64/neon/generated.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -17158,7 +17158,7 @@ pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 {
let x: i64 = vqaddd_s64(a, vqdmulls_s32(b, c));
x as i64
x
}
#[doc = "Signed saturating doubling multiply-subtract long"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"]
Expand Down Expand Up @@ -17324,7 +17324,7 @@ pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 {
let x: i64 = vqsubd_s64(a, vqdmulls_s32(b, c));
x as i64
x
}
#[doc = "Vector saturating doubling multiply high by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"]
Expand Down Expand Up @@ -19495,10 +19495,7 @@ pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
#[cfg_attr(test, assert_instr(tbl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t {
unsafe {
let x = transmute(vqtbl1(transmute(a), b));
x
}
unsafe { transmute(vqtbl1(transmute(a), b)) }
}
#[doc = "Table look-up"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"]
Expand All @@ -19507,10 +19504,7 @@ pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t {
#[cfg_attr(test, assert_instr(tbl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
unsafe {
let x = transmute(vqtbl1q(transmute(a), b));
x
}
unsafe { transmute(vqtbl1q(transmute(a), b)) }
}
#[doc = "Table look-up"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"]
Expand All @@ -19519,10 +19513,7 @@ pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
#[cfg_attr(test, assert_instr(tbl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t {
unsafe {
let x = transmute(vqtbl1(transmute(a), b));
x
}
unsafe { transmute(vqtbl1(transmute(a), b)) }
}
#[doc = "Table look-up"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"]
Expand All @@ -19531,10 +19522,7 @@ pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t {
#[cfg_attr(test, assert_instr(tbl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
unsafe {
let x = transmute(vqtbl1q(transmute(a), b));
x
}
unsafe { transmute(vqtbl1q(transmute(a), b)) }
}
#[doc = "Table look-up"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"]
Expand Down Expand Up @@ -20397,10 +20385,7 @@ pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
#[cfg_attr(test, assert_instr(tbx))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t {
unsafe {
let x = transmute(vqtbx1(transmute(a), transmute(b), c));
x
}
unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) }
}
#[doc = "Extended table look-up"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"]
Expand All @@ -20409,10 +20394,7 @@ pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t {
#[cfg_attr(test, assert_instr(tbx))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
unsafe {
let x = transmute(vqtbx1q(transmute(a), transmute(b), c));
x
}
unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) }
}
#[doc = "Extended table look-up"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"]
Expand All @@ -20421,10 +20403,7 @@ pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
#[cfg_attr(test, assert_instr(tbx))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t {
unsafe {
let x = transmute(vqtbx1(transmute(a), transmute(b), c));
x
}
unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) }
}
#[doc = "Extended table look-up"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"]
Expand All @@ -20433,10 +20412,7 @@ pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t {
#[cfg_attr(test, assert_instr(tbx))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t {
unsafe {
let x = transmute(vqtbx1q(transmute(a), transmute(b), c));
x
}
unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) }
}
#[doc = "Extended table look-up"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"]
Expand Down
104 changes: 14 additions & 90 deletions crates/core_arch/src/arm_shared/neon/generated.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -40758,16 +40758,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")]
fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
}
unsafe {
_vqshlu_n_s8(
a,
const {
int8x8_t([
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
])
},
)
}
unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
Expand All @@ -40783,17 +40774,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")]
fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
}
unsafe {
_vqshluq_n_s8(
a,
const {
int8x16_t([
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
])
},
)
}
unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
Expand All @@ -40809,12 +40790,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")]
fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
}
unsafe {
_vqshlu_n_s16(
a,
const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
)
}
unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
Expand All @@ -40830,16 +40806,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")]
fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
}
unsafe {
_vqshluq_n_s16(
a,
const {
int16x8_t([
N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
])
},
)
}
unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
Expand All @@ -40855,7 +40822,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")]
fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
}
unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
Expand All @@ -40871,12 +40838,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")]
fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
}
unsafe {
_vqshluq_n_s32(
a,
const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
)
}
unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
Expand Down Expand Up @@ -40908,7 +40870,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")]
fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
}
unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
Expand All @@ -40927,16 +40889,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
)]
fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
}
unsafe {
_vqshlu_n_s8(
a,
const {
int8x8_t([
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
])
},
)
}
unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
Expand All @@ -40955,17 +40908,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
)]
fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
}
unsafe {
_vqshluq_n_s8(
a,
const {
int8x16_t([
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
])
},
)
}
unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
Expand All @@ -40984,12 +40927,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
)]
fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
}
unsafe {
_vqshlu_n_s16(
a,
const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
)
}
unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
Expand All @@ -41008,16 +40946,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
)]
fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
}
unsafe {
_vqshluq_n_s16(
a,
const {
int16x8_t([
N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
])
},
)
}
unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
Expand All @@ -41036,7 +40965,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
)]
fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
}
unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
Expand All @@ -41055,12 +40984,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
)]
fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
}
unsafe {
_vqshluq_n_s32(
a,
const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
)
}
unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) }
}
#[doc = "Signed saturating shift left unsigned"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
Expand Down Expand Up @@ -41098,7 +41022,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
)]
fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
}
unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) }
}
#[doc = "Signed saturating shift right narrow"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
Expand Down
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