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Adding abdu/abds to canCreateUndefOrPoison #149017

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Merged
merged 3 commits into from
Jul 18, 2025
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Merged

Adding abdu/abds to canCreateUndefOrPoison #149017

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c2bd312
abdu/abds to canCreateUndefOrPoison
AnnuCode Jul 16, 2025
20cfaeb
updating tests
AnnuCode Jul 18, 2025
81d7fef
Merge branch 'main' into 147695_fix
RKSimon Jul 18, 2025
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2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5544,6 +5544,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::USUBSAT:
case ISD::MULHU:
case ISD::MULHS:
case ISD::ABDU:
case ISD::ABDS:
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
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34 changes: 34 additions & 0 deletions llvm/test/CodeGen/AArch64/freeze.ll
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Expand Up @@ -395,3 +395,37 @@ define i64 @freeze_array() {
%t1 = add i64 %v1, %v2
ret i64 %t1
}

define <8 x i16> @freeze_abdu(<8 x i16> %a, <8 x i16> %b) {
; CHECK-SD-LABEL: freeze_abdu:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: uaba v0.8h, v0.8h, v1.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: freeze_abdu:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: uabd v1.8h, v0.8h, v1.8h
; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h
; CHECK-GI-NEXT: ret
%d = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %a, <8 x i16> %b)
%f = freeze <8 x i16> %d
%r = add <8 x i16> %a, %f
ret <8 x i16> %r
}
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This isn't testing anything yet - we need to use the aarch64 @llvm.aarch64.neon.?abd.* intrinsics directly to ensure we start from a ABDU/S node (look at arm64-vabs.ll for examples). We then need to prove that the freeze has been moved - something similar to what I've proposed for the AVG nodes here: #148191 (comment)


define <8 x i16> @freeze_abds(<8 x i16> %a, <8 x i16> %b) {
; CHECK-SD-LABEL: freeze_abds:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: saba v0.8h, v0.8h, v1.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: freeze_abds:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sabd v1.8h, v0.8h, v1.8h
; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h
; CHECK-GI-NEXT: ret
%d = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %a, <8 x i16> %b)
%f = freeze <8 x i16> %d
%r = add <8 x i16> %a, %f
ret <8 x i16> %r
}