Adding abdu/abds to canCreateUndefOrPoison #149017

AnnuCode · 2025-07-16T04:26:42Z

github-actions · 2025-07-16T04:27:00Z

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llvmbot · 2025-07-16T04:27:33Z

@llvm/pr-subscribers-llvm-selectiondag

Author: Annu Singh (AnnuCode)

Changes

Fixes #147695

Full diff: https://github.com/llvm/llvm-project/pull/149017.diff

2 Files Affected:

(modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+2)
(modified) llvm/test/CodeGen/AArch64/freeze.ll (+48)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 70a39eab1e720..11028cae2e43a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5619,6 +5619,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   case ISD::ADD:
   case ISD::SUB:
   case ISD::MUL:
+  case ISD::ABDU:
+  case ISD::ABDS:
   case ISD::FNEG:
   case ISD::FADD:
   case ISD::FSUB:
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index 0c56e1b66e81f..63ee03e36efb2 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -395,3 +395,51 @@ define i64 @freeze_array() {
   %t1 = add i64 %v1, %v2
   ret i64 %t1
 }
+
+define i32 @freeze_abdu(i8 %x, i8 %y) {
+; CHECK-SD-LABEL: freeze_abdu:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w8, w0, #0xff
+; CHECK-SD-NEXT:    sub w8, w8, w1, uxtb
+; CHECK-SD-NEXT:    cmp w8, #0
+; CHECK-SD-NEXT:    cneg w0, w8, mi
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: freeze_abdu:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0xff
+; CHECK-GI-NEXT:    sub w8, w8, w1, uxtb
+; CHECK-GI-NEXT:    cmp w8, #0
+; CHECK-GI-NEXT:    cneg w0, w8, le
+; CHECK-GI-NEXT:    ret
+  %a   = zext   i8 %x to i32
+  %b   = zext   i8 %y to i32
+  %d   = sub    i32 %a, %b
+  %t   = call   i32 @llvm.abs.i32(i32 %d, i1 false)
+  %f   = freeze i32 %t
+  ret  i32 %f
+}
+
+define i32 @freeze_abds(i8 %x, i8 %y) {
+; CHECK-SD-LABEL: freeze_abds:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    sxtb w8, w0
+; CHECK-SD-NEXT:    sub w8, w8, w1, sxtb
+; CHECK-SD-NEXT:    cmp w8, #0
+; CHECK-SD-NEXT:    cneg w0, w8, mi
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: freeze_abds:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sxtb w8, w0
+; CHECK-GI-NEXT:    sub w8, w8, w1, sxtb
+; CHECK-GI-NEXT:    cmp w8, #0
+; CHECK-GI-NEXT:    cneg w0, w8, le
+; CHECK-GI-NEXT:    ret
+  %a = sext i8 %x to i32
+  %b = sext i8 %y to i32
+  %d = sub i32 %a, %b
+  %abs = call i32 @llvm.abs.i32(i32 %d, i1 true)
+  %f = freeze i32 %abs
+  ret i32 %f
+}

llvmbot · 2025-07-16T04:27:34Z

@llvm/pr-subscribers-backend-aarch64

Author: Annu Singh (AnnuCode)

Changes

Fixes #147695

Full diff: https://github.com/llvm/llvm-project/pull/149017.diff

2 Files Affected:

(modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+2)
(modified) llvm/test/CodeGen/AArch64/freeze.ll (+48)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 70a39eab1e720..11028cae2e43a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5619,6 +5619,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   case ISD::ADD:
   case ISD::SUB:
   case ISD::MUL:
+  case ISD::ABDU:
+  case ISD::ABDS:
   case ISD::FNEG:
   case ISD::FADD:
   case ISD::FSUB:
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index 0c56e1b66e81f..63ee03e36efb2 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -395,3 +395,51 @@ define i64 @freeze_array() {
   %t1 = add i64 %v1, %v2
   ret i64 %t1
 }
+
+define i32 @freeze_abdu(i8 %x, i8 %y) {
+; CHECK-SD-LABEL: freeze_abdu:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w8, w0, #0xff
+; CHECK-SD-NEXT:    sub w8, w8, w1, uxtb
+; CHECK-SD-NEXT:    cmp w8, #0
+; CHECK-SD-NEXT:    cneg w0, w8, mi
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: freeze_abdu:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0xff
+; CHECK-GI-NEXT:    sub w8, w8, w1, uxtb
+; CHECK-GI-NEXT:    cmp w8, #0
+; CHECK-GI-NEXT:    cneg w0, w8, le
+; CHECK-GI-NEXT:    ret
+  %a   = zext   i8 %x to i32
+  %b   = zext   i8 %y to i32
+  %d   = sub    i32 %a, %b
+  %t   = call   i32 @llvm.abs.i32(i32 %d, i1 false)
+  %f   = freeze i32 %t
+  ret  i32 %f
+}
+
+define i32 @freeze_abds(i8 %x, i8 %y) {
+; CHECK-SD-LABEL: freeze_abds:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    sxtb w8, w0
+; CHECK-SD-NEXT:    sub w8, w8, w1, sxtb
+; CHECK-SD-NEXT:    cmp w8, #0
+; CHECK-SD-NEXT:    cneg w0, w8, mi
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: freeze_abds:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sxtb w8, w0
+; CHECK-GI-NEXT:    sub w8, w8, w1, sxtb
+; CHECK-GI-NEXT:    cmp w8, #0
+; CHECK-GI-NEXT:    cneg w0, w8, le
+; CHECK-GI-NEXT:    ret
+  %a = sext i8 %x to i32
+  %b = sext i8 %y to i32
+  %d = sub i32 %a, %b
+  %abs = call i32 @llvm.abs.i32(i32 %d, i1 true)
+  %f = freeze i32 %abs
+  ret i32 %f
+}

RKSimon · 2025-07-16T07:19:03Z

llvm/test/CodeGen/AArch64/freeze.ll

+  %t   = call   i32 @llvm.abs.i32(i32 %d, i1 false)
+  %f   = freeze i32 %t
+  ret  i32 %f
+}


This isn't testing anything yet - we need to use the aarch64 @llvm.aarch64.neon.?abd.* intrinsics directly to ensure we start from a ABDU/S node (look at arm64-vabs.ll for examples). We then need to prove that the freeze has been moved - something similar to what I've proposed for the AVG nodes here: #148191 (comment)

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

AnnuCode · 2025-07-18T06:27:05Z

@RKSimon I've made changes as per suggestion. Can you please check if they are correct?

The Alive2 test says: Unknown libcall: @llvm.aarch64.neon.sabd.v2i8

RKSimon · 2025-07-18T08:17:27Z

Thanks @AnnuCode - for the alive2 tests you can test with the generic pattern, although you need to account for the final truncation as well for completeness:

define i4 @src(i4 %x, i4 %y) {
entry:
  %a   = zext   i4 %x to i8
  %b   = zext   i4 %y to i8
  %d   = sub    i8 %a, %b
  %t   = call   i8 @llvm.abs.i8(i8 %d, i1 false)
  %r   = trunc i8 %t to i4
  %f   = freeze i4 %r
  ret  i4 %f
}

define i4 @tgt(i4 %x, i4 %y) {
entry:
  %fx  = freeze i4 %x
  %fy  = freeze i4 %y
  %a1  = zext   i4 %fx to i8
  %b1  = zext   i4 %fy to i8
  %d1  = sub    i8 %a1, %b1
  %t1  = call   i8 @llvm.abs.i8(i8 %d1, i1 false)
  %r1  = trunc i8 %t1 to i4
  ret  i4 %r1
}

AnnuCode · 2025-07-18T11:16:47Z

@RKSimon thanks! Now I understand why to include final truncation in the Alive2 tests, as it completes the generic pattern of abdu/s. Here are the tests:

RKSimon

LGTM - cheers!

github-actions · 2025-07-18T16:01:01Z

@AnnuCode Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

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abdu/abds to canCreateUndefOrPoison

c2bd312

llvmbot added backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well labels Jul 16, 2025

RKSimon requested review from davemgreen and RKSimon July 16, 2025 07:11

RKSimon reviewed Jul 16, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Outdated Show resolved Hide resolved

updating tests

20cfaeb

RKSimon approved these changes Jul 18, 2025

View reviewed changes

Merge branch 'main' into 147695_fix

81d7fef

RKSimon merged commit 148fd6e into llvm:main Jul 18, 2025
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Adding abdu/abds to canCreateUndefOrPoison #149017

Adding abdu/abds to canCreateUndefOrPoison #149017

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Adding abdu/abds to canCreateUndefOrPoison #149017

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