[InstCombine] Optimize (select %x, op(%x), 0) to op(%x) for operations where op(0) == 0 #147605

bababuck · 2025-07-08T22:23:21Z

Currently this optimization only occurs for mul, but this generalizes that for any operation that has a fixed point of 0.

There is similar logic within EarlyCSE pass, but that is stricter in terms of poison propagation so will not optimize for many operations.

Alive2 Proofs:
and:
https://alive2.llvm.org/ce/z/RraasX ; base-case
https://alive2.llvm.org/ce/z/gzfFTX ; commuted-case
https://alive2.llvm.org/ce/z/63XaoX ; compare against undef
https://alive2.llvm.org/ce/z/MVRVNd ; select undef
https://alive2.llvm.org/ce/z/2bsoYG ; vector
https://alive2.llvm.org/ce/z/xByeX- ; vector compare against undef
https://alive2.llvm.org/ce/z/zNdzmZ ; vector select undef

fshl:
https://alive2.llvm.org/ce/z/U3_PG3 ; base-case
https://alive2.llvm.org/ce/z/BWCnxT ; compare against undef
https://alive2.llvm.org/ce/z/8HGAE_ ; select undef
; vector times out

fshr:
https://alive2.llvm.org/ce/z/o6F47G ; base-case
https://alive2.llvm.org/ce/z/fVnBXy ; compare against undef
https://alive2.llvm.org/ce/z/suymYJ ; select undef
; vector times out

umin:
https://alive2.llvm.org/ce/z/GGMqf6 ; base-case
https://alive2.llvm.org/ce/z/6cx5-k ; commuted-case
https://alive2.llvm.org/ce/z/W5d9tz ; compare against undef
https://alive2.llvm.org/ce/z/nKbaUn ; select undef
https://alive2.llvm.org/ce/z/gxEGqc ; vector
https://alive2.llvm.org/ce/z/_SDpi_ ; vector compare against undef

sdiv:
https://alive2.llvm.org/ce/z/5XGs3q

srem:
https://alive2.llvm.org/ce/z/vXAnQM

udiv:
https://alive2.llvm.org/ce/z/e6_8Ug

urem:
https://alive2.llvm.org/ce/z/VmM2SL

shl:
https://alive2.llvm.org/ce/z/aCZr3u ; Argument with range
https://alive2.llvm.org/ce/z/YgDy8C ; Instruction with known bits
https://alive2.llvm.org/ce/z/6pIxR6 ; Constant

lshr:
https://alive2.llvm.org/ce/z/WCCBej

`ashr:
https://alive2.llvm.org/ce/z/egV4TR

…op(0) == 0 These cases can be optimized to just op(%x).

…s where op(0) == 0 Have to freeze the any other operands to prevent poisons from leaking. Re-uses flow from `mul` specific version of this within the InstCombie pass.

llvmbot · 2025-07-08T22:23:55Z

@llvm/pr-subscribers-llvm-transforms

Author: Ryan Buchner (bababuck)

Changes

Currently this optimization only occurs for mul, but this generalizes that for any operation that has a fixed point of 0.

There is similar logic within EarlyCSE pass, but that is stricter in terms of poison propagation so will not optimize for many operations.

Full diff: https://github.com/llvm/llvm-project/pull/147605.diff

4 Files Affected:

(modified) llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp (+29-10)
(modified) llvm/test/Transforms/InstCombine/icmp-select.ll (+3-4)
(added) llvm/test/Transforms/InstCombine/select-fixed-zero.ll (+170)
(modified) llvm/test/Transforms/InstCombine/select.ll (+6-8)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 73ba0f78e8053..023ca5245f494 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -878,7 +878,11 @@ static Instruction *foldSetClearBits(SelectInst &Sel,
 // is a vector consisting of 0 and undefs. If a constant compared with x
 // is a scalar undefined value or undefined vector then an expression
 // should be already folded into a constant.
-static Instruction *foldSelectZeroOrMul(SelectInst &SI, InstCombinerImpl &IC) {
+//
+// This also holds all operations such that Op(0) == 0
+// e.g. Shl, Umin, etc
+static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
+                                            InstCombinerImpl &IC) {
   auto *CondVal = SI.getCondition();
   auto *TrueVal = SI.getTrueValue();
   auto *FalseVal = SI.getFalseValue();
@@ -900,9 +904,7 @@ static Instruction *foldSelectZeroOrMul(SelectInst &SI, InstCombinerImpl &IC) {
   // non-zero elements that are masked by undef elements in the compare
   // constant.
   auto *TrueValC = dyn_cast<Constant>(TrueVal);
-  if (TrueValC == nullptr ||
-      !match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
-      !isa<Instruction>(FalseVal))
+  if (TrueValC == nullptr || !isa<Instruction>(FalseVal))
     return nullptr;
 
   auto *ZeroC = cast<Constant>(cast<Instruction>(CondVal)->getOperand(1));
@@ -913,11 +915,28 @@ static Instruction *foldSelectZeroOrMul(SelectInst &SI, InstCombinerImpl &IC) {
   if (!match(MergedC, m_Zero()) && !match(MergedC, m_Undef()))
     return nullptr;
 
-  auto *FalseValI = cast<Instruction>(FalseVal);
-  auto *FrY = IC.InsertNewInstBefore(new FreezeInst(Y, Y->getName() + ".fr"),
-                                     FalseValI->getIterator());
-  IC.replaceOperand(*FalseValI, FalseValI->getOperand(0) == Y ? 0 : 1, FrY);
-  return IC.replaceInstUsesWith(SI, FalseValI);
+  if (match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_Shl(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_AShr(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_LShr(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_UDiv(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_c_UMin(m_Specific(X), m_Value(Y)))) {
+    auto *FalseValI = cast<Instruction>(FalseVal);
+    auto *FrY = IC.InsertNewInstBefore(new FreezeInst(Y, Y->getName() + ".fr"),
+                                       FalseValI->getIterator());
+    IC.replaceOperand(*FalseValI,
+                      FalseValI->getOperand(0) == Y
+                          ? 0
+                          : (FalseValI->getOperand(1) == Y ? 1 : 2),
+                      FrY);
+    return IC.replaceInstUsesWith(SI, FalseValI);
+  }
+
+  return nullptr;
 }
 
 /// Transform patterns such as (a > b) ? a - b : 0 into usub.sat(a, b).
@@ -4104,7 +4123,7 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
     return Add;
   if (Instruction *Or = foldSetClearBits(SI, Builder))
     return Or;
-  if (Instruction *Mul = foldSelectZeroOrMul(SI, *this))
+  if (Instruction *Mul = foldSelectZeroOrFixedOp(SI, *this))
     return Mul;
 
   // Turn (select C, (op X, Y), (op X, Z)) -> (op X, (select C, Y, Z))
diff --git a/llvm/test/Transforms/InstCombine/icmp-select.ll b/llvm/test/Transforms/InstCombine/icmp-select.ll
index a038731abbc48..c6c0ba385a6fd 100644
--- a/llvm/test/Transforms/InstCombine/icmp-select.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-select.ll
@@ -248,10 +248,9 @@ define i1 @icmp_select_implied_cond_relational_off_by_one(i8 %x, i8 %y) {
 
 define i1 @umin_seq_comparison(i8 %x, i8 %y) {
 ; CHECK-LABEL: @umin_seq_comparison(
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[CMP21:%.*]] = icmp ule i8 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP2:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP21]]
-; CHECK-NEXT:    ret i1 [[CMP2]]
+; CHECK-NEXT:    [[Y:%.*]] = freeze i8 [[Y1:%.*]]
+; CHECK-NEXT:    [[CMP21:%.*]] = icmp ule i8 [[X:%.*]], [[Y]]
+; CHECK-NEXT:    ret i1 [[CMP21]]
 ;
   %min = call i8 @llvm.umin.i8(i8 %x, i8 %y)
   %cmp1 = icmp eq i8 %x, 0
diff --git a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
new file mode 100644
index 0000000000000..b41f443d6131e
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
@@ -0,0 +1,170 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s --check-prefix=FIXED-ZERO
+
+; (select (icmp x, 0, eq), 0, (umin x, y)) -> (umin x, y)
+define i64 @umin_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @umin_select(
+; FIXED-ZERO-NEXT:    [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; FIXED-ZERO-NEXT:    [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[A:%.*]], i64 [[B_FR]])
+; FIXED-ZERO-NEXT:    ret i64 [[UMIN]]
+;
+  %cond = icmp eq i64 %a, 0
+  %umin = call i64 @llvm.umin.i64(i64 %a, i64 %b)
+  %select = select i1 %cond, i64 0, i64 %umin
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (mul x, y)) -> (mul x, y)
+define i64 @mul_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @mul_select(
+; FIXED-ZERO-NEXT:    [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; FIXED-ZERO-NEXT:    [[MUL:%.*]] = mul i64 [[A:%.*]], [[B_FR]]
+; FIXED-ZERO-NEXT:    ret i64 [[MUL]]
+;
+  %cond = icmp eq i64 %a, 0
+  %mul = mul i64 %a, %b
+  %select = select i1 %cond, i64 0, i64 %mul
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (shl x, y)) -> (shl x, y)
+define i64 @shl_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @shl_select(
+; FIXED-ZERO-NEXT:    [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; FIXED-ZERO-NEXT:    [[SHL:%.*]] = shl i64 [[A:%.*]], [[B_FR]]
+; FIXED-ZERO-NEXT:    ret i64 [[SHL]]
+;
+  %cond = icmp eq i64 %a, 0
+  %shl = shl i64 %a, %b
+  %select = select i1 %cond, i64 0, i64 %shl
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (and x, y)) -> (and x, y)
+define i64 @and_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @and_select(
+; FIXED-ZERO-NEXT:    [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; FIXED-ZERO-NEXT:    [[AND:%.*]] = and i64 [[A:%.*]], [[B_FR]]
+; FIXED-ZERO-NEXT:    ret i64 [[AND]]
+;
+  %cond = icmp eq i64 %a, 0
+  %and = and i64 %a, %b
+  %select = select i1 %cond, i64 0, i64 %and
+  ret i64 %select
+}
+
+; (select (icmp x, 0, ne), (ashr x, y), 0) -> (ashr x, y)
+define i64 @ashr_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @ashr_select(
+; FIXED-ZERO-NEXT:    [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; FIXED-ZERO-NEXT:    [[ASHR:%.*]] = ashr i64 [[A:%.*]], [[B_FR]]
+; FIXED-ZERO-NEXT:    ret i64 [[ASHR]]
+;
+  %cond = icmp ne i64 0, %a
+  %ashr = ashr i64 %a, %b
+  %select = select i1 %cond, i64 %ashr, i64 0
+  ret i64 %select
+}
+
+; (select (icmp x, 0, ne), (lshr x, y), 0) -> (lshr x, y)
+define i64 @lshr_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @lshr_select(
+; FIXED-ZERO-NEXT:    [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; FIXED-ZERO-NEXT:    [[LSHR:%.*]] = lshr i64 [[A:%.*]], [[B_FR]]
+; FIXED-ZERO-NEXT:    ret i64 [[LSHR]]
+;
+  %cond = icmp ne i64 0, %a
+  %lshr = lshr i64 %a, %b
+  %select = select i1 %cond, i64 %lshr, i64 0
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, fshr(x, x, y)) -> fshr(x, x, y)
+define i64 @fshr_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @fshr_select(
+; FIXED-ZERO-NEXT:    [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; FIXED-ZERO-NEXT:    [[FSHR:%.*]] = call i64 @llvm.fshr.i64(i64 [[A:%.*]], i64 [[A]], i64 [[B_FR]])
+; FIXED-ZERO-NEXT:    ret i64 [[FSHR]]
+;
+  %cond = icmp eq i64 %a, 0
+  %fshr = call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
+  %select = select i1 %cond, i64 0, i64 %fshr
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (fshl x, x, y)) -> (fshl x, x, y)
+define i64 @fshl_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @fshl_select(
+; FIXED-ZERO-NEXT:    [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; FIXED-ZERO-NEXT:    [[FSHL:%.*]] = call i64 @llvm.fshl.i64(i64 [[A:%.*]], i64 [[A]], i64 [[B_FR]])
+; FIXED-ZERO-NEXT:    ret i64 [[FSHL]]
+;
+  %cond = icmp eq i64 %a, 0
+  %fshl = call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
+  %select = select i1 %cond, i64 0, i64 %fshl
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (fshr x, z, y)) -> leave as is
+define i64 @fshr_select_no_combine(i64 %a, i64 %b, i64 %c) {
+; FIXED-ZERO-LABEL: @fshr_select_no_combine(
+; FIXED-ZERO-NEXT:    [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; FIXED-ZERO-NEXT:    [[FSHR:%.*]] = call i64 @llvm.fshr.i64(i64 [[A]], i64 [[B:%.*]], i64 [[C:%.*]])
+; FIXED-ZERO-NEXT:    [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[FSHR]]
+; FIXED-ZERO-NEXT:    ret i64 [[SELECT]]
+;
+  %cond = icmp eq i64 %a, 0
+  %fshr = call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
+  %select = select i1 %cond, i64 0, i64 %fshr
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (sdiv x, y)) -> (sdiv x, y)
+define i64 @sdiv_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @sdiv_select(
+; FIXED-ZERO-NEXT:    [[B:%.*]] = freeze i64 [[B1:%.*]]
+; FIXED-ZERO-NEXT:    [[DIV:%.*]] = sdiv i64 [[A:%.*]], [[B]]
+; FIXED-ZERO-NEXT:    ret i64 [[DIV]]
+;
+  %cond = icmp eq i64 %a, 0
+  %div = sdiv i64 %a, %b
+  %select = select i1 %cond, i64 0, i64 %div
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (udiv x, y)) -> (udiv x, y)
+define i64 @udiv_select(i64 %a, i64 %b) {
+; FIXED-ZERO-LABEL: @udiv_select(
+; FIXED-ZERO-NEXT:    [[B:%.*]] = freeze i64 [[B1:%.*]]
+; FIXED-ZERO-NEXT:    [[DIV:%.*]] = udiv i64 [[A:%.*]], [[B]]
+; FIXED-ZERO-NEXT:    ret i64 [[DIV]]
+;
+  %cond = icmp eq i64 %a, 0
+  %div = udiv i64 %a, %b
+  %select = select i1 %cond, i64 0, i64 %div
+  ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (icmp x, 0, slt)) -> (icmp x, 0, slt)
+define i1 @icmp_slt_select(i64 %a) {
+; FIXED-ZERO-LABEL: @icmp_slt_select(
+; FIXED-ZERO-NEXT:    [[ICMP:%.*]] = icmp slt i64 [[A:%.*]], 0
+; FIXED-ZERO-NEXT:    ret i1 [[ICMP]]
+;
+  %cond = icmp eq i64 %a, 0
+  %icmp = icmp slt i64 %a, 0
+  %select = select i1 %cond, i1 0, i1 %icmp
+  ret i1 %select
+}
+
+; (select (icmp x, 0, eq), 0, (sub 0, x)) -> (sub 0, x)
+define i64 @sub_select(i64 %a) {
+; FIXED-ZERO-LABEL: @sub_select(
+; FIXED-ZERO-NEXT:    [[SUB:%.*]] = sub i64 0, [[A:%.*]]
+; FIXED-ZERO-NEXT:    ret i64 [[SUB]]
+;
+  %cond = icmp eq i64 %a, 0
+  %sub = sub i64 0, %a
+  %select = select i1 %cond, i64 0, i64 %sub
+  ret i64 %select
+}
diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index ef5874ffd46ad..fa54b38d55171 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -893,10 +893,9 @@ define i32 @test56(i16 %x) {
 
 define i32 @test57(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test57(
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[X]], 0
-; CHECK-NEXT:    [[DOTAND:%.*]] = select i1 [[TOBOOL]], i32 0, i32 [[AND]]
-; CHECK-NEXT:    ret i32 [[DOTAND]]
+; CHECK-NEXT:    [[Y:%.*]] = freeze i32 [[Y1:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], [[Y]]
+; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %and = and i32 %x, %y
   %tobool = icmp eq i32 %x, 0
@@ -2734,10 +2733,9 @@ define void @select_freeze_icmp_multuses(i32 %x, i32 %y) {
 
 define i32 @pr47322_more_poisonous_replacement(i32 %arg) {
 ; CHECK-LABEL: @pr47322_more_poisonous_replacement(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[ARG:%.*]], 0
-; CHECK-NEXT:    [[TRAILING:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG]], i1 true)
-; CHECK-NEXT:    [[SHIFTED:%.*]] = lshr exact i32 [[ARG]], [[TRAILING]]
-; CHECK-NEXT:    [[R1_SROA_0_1:%.*]] = select i1 [[CMP]], i32 0, i32 [[SHIFTED]]
+; CHECK-NEXT:    [[TRAILING:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG:%.*]], i1 true)
+; CHECK-NEXT:    [[TRAILING_FR:%.*]] = freeze i32 [[TRAILING]]
+; CHECK-NEXT:    [[R1_SROA_0_1:%.*]] = lshr exact i32 [[ARG]], [[TRAILING_FR]]
 ; CHECK-NEXT:    ret i32 [[R1_SROA_0_1]]
 ;
   %cmp = icmp eq i32 %arg, 0

dtcxzyw · 2025-07-09T05:13:17Z

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

-  return IC.replaceInstUsesWith(SI, FalseValI);
+  if (match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_Shl(m_Specific(X), m_Value(Y))) ||


It doesn't work for shift operators. shl 0, freeze(poison) can be poison when shamt is invalid.

Thanks, I will remove shl, ashr and lshr.

From what I can tell, fshl and fshr intrinsics do not have this issue so they can remain. Is that correct?

Yes, fshl/fshr shifts are modulo the bitwidth.

If I wanted to perform this transformation on the shift operators (shl, ashr, lshr), should that get done during target specific lowering (i.e. RISCV sll instruction uses modulo bitwidth for shamt)?

If I wanted to perform this transformation on the shift operators (shl, ashr, lshr), should that get done during target specific lowering (i.e. RISCV sll instruction uses modulo bitwidth for shamt)?

You can check if Y is never poison with isGuaranteedNotTobePoison.

and/mul: valid with freeze(Y) if Y may be poison
shl/lshr/ashr: valid if Y cannot be poison
udiv/sdiv/urem/srem: always valid without freeze

I am going to leave the shift's out from this MR for the following reason. For shift operations, if the inputs are guaranteed not to be poison, whether or not the operation isGuaranteedNotToBePoison boils down to the shamt, and a function call to static bool shiftAmountKnownInRange(const Value *ShiftAmount), which checks if the shamt is a Constant smaller than the bit-width.

However, there is an existing transformation in InstCombine that handles the cases for which the shamt is a constant, so it seems redundant to include it here.

A separate note, if we could get static bool shiftAmountKnownInRange(const Value *ShiftAmount) access to information about Value's ranges (i.e. range(i64 0 10)) it would be effective in more situations.

I think we can start with constant (splat) shamts (i.e., use m_APInt(C) and C->ult(BW)).

A separate note, if we could get static bool shiftAmountKnownInRange(const Value *ShiftAmount) access to information about Value's ranges (i.e. range(i64 0 10)) it would be effective in more situations.

If you want to handle variable shamts, use computeKnownBits().getMaxValue().ult(BW).

I updated static bool shiftAmountKnownInRange(const Value *ShiftAmount) to handle variable shamts, both from instructions using computeknownbits and arguments using getRange(). This should probably go in its own MR though.

I added back the logic for shl/ashr/lshr for cases where the shift amount is predictable.

Am adding the alive2 proofs for these to the MR description.

Can we please keep the shift case out of this patch? It requires changing generic ValueTracking APIs, and we need to evaluate the impact of that separately.

I'll remove it here and then create a separate MR for that once this gets merged.

dtcxzyw · 2025-07-09T05:22:17Z

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

-  if (TrueValC == nullptr ||
-      !match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
-      !isa<Instruction>(FalseVal))
+  if (TrueValC == nullptr || !isa<Instruction>(FalseVal))


Crash reproducer:

; bin/opt -passes=instcombine test.ll -S target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-linux-gnu" define <2 x i64> @php_url_encode_impl(i32 %0, ptr %p) { %2 = load <2 x i64>, ptr %p, align 16 %.not = icmp eq i32 %0, 0 %spec.select = select i1 %.not, <2 x i64> zeroinitializer, <2 x i64> %2 ret <2 x i64> %spec.select }

opt: /home/dtcxzyw/WorkSpace/Projects/compilers/llvm-project/llvm/lib/IR/Constants.cpp:823: static llvm::Constant* llvm::Constant::mergeUndefsWith(llvm::Constant*, llvm::Constant*): Assertion `isa<FixedVectorType>(Other->getType()) && cast<FixedVectorType>(Other->getType())->getNumElements() == NumElts && "Type mismatch"' failed. PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. Stack dump: 0. Program arguments: bin/opt -passes=instcombine reduced.ll -S 1. Running pass "function(instcombine<max-iterations=1;verify-fixpoint>)" on module "reduced.ll" 2. Running pass "instcombine<max-iterations=1;verify-fixpoint>" on function "php_url_encode_impl" #0 0x0000727c5de283e2 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/libLLVMSupport.so.21.0git+0x2283e2) #1 0x0000727c5de249ef llvm::sys::RunSignalHandlers() (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/libLLVMSupport.so.21.0git+0x2249ef) #2 0x0000727c5de24b34 SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 #3 0x0000727c5d845330 (/lib/x86_64-linux-gnu/libc.so.6+0x45330) #4 0x0000727c5d89eb2c __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 #5 0x0000727c5d89eb2c __pthread_kill_internal ./nptl/pthread_kill.c:78:10 #6 0x0000727c5d89eb2c pthread_kill ./nptl/pthread_kill.c:89:10 #7 0x0000727c5d84527e raise ./signal/../sysdeps/posix/raise.c:27:6 #8 0x0000727c5d8288ff abort ./stdlib/abort.c:81:7 #9 0x0000727c5d82881b _nl_load_domain ./intl/loadmsgcat.c:1177:9 #10 0x0000727c5d83b517 (/lib/x86_64-linux-gnu/libc.so.6+0x3b517) #11 0x0000727c54587344 llvm::Constant::mergeUndefsWith(llvm::Constant*, llvm::Constant*) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMCore.so.21.0git+0x187344) #12 0x0000727c55969950 foldSelectZeroOrFixedOp(llvm::SelectInst&, llvm::InstCombinerImpl&) InstCombineSelect.cpp:0:0 #13 0x0000727c559709d0 llvm::InstCombinerImpl::visitSelectInst(llvm::SelectInst&) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMInstCombine.so.21.0git+0x16f9d0) #14 0x0000727c55869c18 llvm::InstCombinerImpl::run() (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMInstCombine.so.21.0git+0x68c18) #15 0x0000727c5586ad7f combineInstructionsOverFunction(llvm::Function&, llvm::InstructionWorklist&, llvm::AAResults*, llvm::AssumptionCache&, llvm::TargetLibraryInfo&, llvm::TargetTransformInfo&, llvm::DominatorTree&, llvm::OptimizationRemarkEmitter&, llvm::BlockFrequencyInfo*, llvm::BranchProbabilityInfo*, llvm::ProfileSummaryInfo*, llvm::InstCombineOptions const&) InstructionCombining.cpp:0:0 #16 0x0000727c5586bde4 llvm::InstCombinePass::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMInstCombine.so.21.0git+0x6ade4) #17 0x0000727c57daa635 llvm::detail::PassModel<llvm::Function, llvm::InstCombinePass, llvm::AnalysisManager<llvm::Function>>::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libPolly.so.21.0git+0x1aa635) #18 0x0000727c54733a15 llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMCore.so.21.0git+0x333a15) #19 0x0000727c5c8da9b5 llvm::detail::PassModel<llvm::Function, llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>, llvm::AnalysisManager<llvm::Function>>::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMX86CodeGen.so.21.0git+0xda9b5) #20 0x0000727c54733e12 llvm::ModuleToFunctionPassAdaptor::run(llvm::Module&, llvm::AnalysisManager<llvm::Module>&) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMCore.so.21.0git+0x333e12) #21 0x0000727c5c8db375 llvm::detail::PassModel<llvm::Module, llvm::ModuleToFunctionPassAdaptor, llvm::AnalysisManager<llvm::Module>>::run(llvm::Module&, llvm::AnalysisManager<llvm::Module>&) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMX86CodeGen.so.21.0git+0xdb375) #22 0x0000727c54734fed llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>::run(llvm::Module&, llvm::AnalysisManager<llvm::Module>&) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/../lib/libLLVMCore.so.21.0git+0x334fed) #23 0x0000727c5df8e309 llvm::runPassPipeline(llvm::StringRef, llvm::Module&, llvm::TargetMachine*, llvm::TargetLibraryInfoImpl*, llvm::ToolOutputFile*, llvm::ToolOutputFile*, llvm::ToolOutputFile*, llvm::StringRef, llvm::ArrayRef<llvm::PassPlugin>, llvm::ArrayRef<std::function<void (llvm::PassBuilder&)>>, llvm::opt_tool::OutputKind, llvm::opt_tool::VerifierKind, bool, bool, bool, bool, bool, bool, bool) (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/libLLVMOptDriver.so.21.0git+0x2d309) #24 0x0000727c5df994c2 optMain (/home/dtcxzyw/WorkSpace/Projects/compilers/LLVM/llvm-build/bin/../lib/libLLVMOptDriver.so.21.0git+0x384c2) #25 0x0000727c5d82a1ca __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:74:3 #26 0x0000727c5d82a28b call_init ./csu/../csu/libc-start.c:128:20 #27 0x0000727c5d82a28b __libc_start_main ./csu/../csu/libc-start.c:347:5 #28 0x000059b9a636b095 _start (bin/opt+0x1095) Aborted (core dumped)

Thanks.

The issue was that I moved the pattern match to the end of the function. However, one side effect of the pattern match is that it guarantees that the types of TrueV and the Conditional constant Match which is assumed to be true by:

auto *MergedC = Constant::mergeUndefsWith(TrueValC, ZeroC);

Reordering to perform the pattern matching where it was before this MR solved this issue.

nikic

Can you please add alive2 proofs to the PR description?

llvm/test/Transforms/InstCombine/select-fixed-zero.ll

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

bababuck · 2025-07-09T21:02:56Z

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

+      match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
+      match(FalseVal, m_UDiv(m_Specific(X), m_Value(Y))) ||


Should sdiv and udiv should be removed as well since they can create undef in the case of the denominator being 0? My understanding is that 0 / freeze(y) would be more poisonous than 0 in that case when freeze(y) is 0.

For more context, Alive2 says the [s/u]div transformation is correct.

Should sdiv and udiv should be removed as well since they can create undef in the case of the denominator being 0? My understanding is that 0 / freeze(y) would be more poisonous than 0 in that case when freeze(y) is 0.

It is safe, even without inserting freeze. If Y is poison, it means div/rem X, Y triggers immediate UB before the select. Therefore, Y cannot be poison.

Thanks for the explanation, I appreciate it!

Fixes bug in optimizing: ``` define <2 x i64> @php_url_encode_impl(i32 %0, ptr %p) { %2 = load <2 x i64>, ptr %p, align 16 %.not = icmp eq i32 %0, 0 %spec.select = select i1 %.not, <2 x i64> zeroinitializer, <2 x i64> %2 ret <2 x i64> %spec.select } ``` One side effect of the matching is that it garuntees that the types of the TrueV and the Conditional constant match which is assumed by the later code.

m_c_UMin will also match with an icmp/select pattern which isn't desired here.

Only one RUN so do not need prefix.

… too large we can create a `poison` value

… can create `undef` value

… determining its legality If the upper value of the range is smaller than the bit width, it cannot produce poison.

… legality of shift amounts

nikic · 2025-07-12T10:12:29Z

llvm/lib/Analysis/ValueTracking.cpp

+  if (A) {
+    auto Range = A->getRange();
+    if (Range && Range->getUnsignedMax().ult(
+                     ShiftAmount->getType()->getIntegerBitWidth())) {


This should use getScalarSizeInBits(), otherwise it will crash for vector shifts. Same below.

Ryan Buchner added 2 commits July 8, 2025 13:43

Add tests for cases with (select %x, op(%x), 0) for operations where …

31d8680

…op(0) == 0 These cases can be optimized to just op(%x).

[InstCombine] Optimize (select %x, op(%x), 0) to op(%x) for operation…

7a12f56

…s where op(0) == 0 Have to freeze the any other operands to prevent poisons from leaking. Re-uses flow from `mul` specific version of this within the InstCombie pass.

bababuck requested a review from nikic as a code owner July 8, 2025 22:23

llvmbot added llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms labels Jul 8, 2025

This was referenced Jul 9, 2025

Fuzz PR147605 dtcxzyw/llvm-mutation-based-fuzz-service#73

Open

Task submission dtcxzyw/llvm-opt-benchmark#1312

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zyw-bot mentioned this pull request Jul 9, 2025

pre-commit: PR147605 dtcxzyw/llvm-opt-benchmark#2562

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dtcxzyw requested changes Jul 9, 2025

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dtcxzyw reviewed Jul 9, 2025

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nikic reviewed Jul 9, 2025

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llvm/test/Transforms/InstCombine/select-fixed-zero.ll Outdated Show resolved Hide resolved

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp Outdated Show resolved Hide resolved

bababuck commented Jul 9, 2025

View reviewed changes

bababuck added 13 commits July 9, 2025 16:19

Use m_c_Intrinsic<Intrinisic::umin> instead of m_c_UMin

e08d66e

m_c_UMin will also match with an icmp/select pattern which isn't desired here.

Remove FIXED-ZERO prefix from select-fixed-zero.ll

ed88808

Only one RUN so do not need prefix.

Don't match with shl, ashr, and ashl because if the shfamt is…

252d55f

… too large we can create a `poison` value

Don't match with udiv and sdiv because if the denominator is 0 we…

09536bb

… can create `undef` value

Add tests for URem and SRem

2cdf85f

Add back in SDiv/UDiv/URem/SRem, but don't freeze them

91810fa

[Analysis] Check if the shift amount is an argument with a range when…

6b59964

… determining its legality If the upper value of the range is smaller than the bit width, it cannot produce poison.

Remove old FIXED-ZERO labels from select-fixed-zero.ll

3b1a350

Add tests for shl/ashr/lshr with noundef-range defined shamt's

9b75cf8

Combine Shl/AShr/LShr if the shamt is garunteed to not be poison

3d674ae

Add test for testing legal shift amounts that are instructions

2de452b

[Analysis] Consider instructions with known bits when determining the…

d01d1f2

… legality of shift amounts

nikic reviewed Jul 12, 2025

View reviewed changes

[InstCombine] Optimize (select %x, op(%x), 0) to op(%x) for operations where op(0) == 0 #147605

Are you sure you want to change the base?

[InstCombine] Optimize (select %x, op(%x), 0) to op(%x) for operations where op(0) == 0 #147605

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bababuck commented Jul 8, 2025 •

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bababuck Jul 9, 2025 •

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