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zli87/README.md
  • 👋 Hi, I’m @zli87
  • 👀 I’m interested in ASIC Design Verification of computer arhictecture
  • 🌱 I plan to learn UVM verification, ASIC accelerator, high level synthesis
  • 💞️ I’m looking to collaborate on RTL design/verification
  • 📫 How to reach me: zli87@alumni.ncsu.edu

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  1. Processor-and-Accelerator Processor-and-Accelerator Public

    MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement

    Verilog 9

  2. Architecture-of-Parallel-Computers Architecture-of-Parallel-Computers Public

    Simulator for Coherence protocol, parallel programming acceleration with OpenMP, MPI, Hybrid

    C 3

  3. Wishbone-to-I2C-bus-controller-IP-Verification Wishbone-to-I2C-bus-controller-IP-Verification Public

    ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.

    VHDL 15 5

  4. High_Level_Synthesis_for_FPGAs High_Level_Synthesis_for_FPGAs Public

    This resource comes from UCSD’s 237C Parallel Programming for FPGAs. Currently, try to finish this tutorial through vitis_hls 2020.

    VHDL 1

  5. Microprocessor-Architecture Microprocessor-Architecture Public

    Cache_Simulator, Branch_Prediction and Dynamic_Instruction_Scheduling

    C++ 1

  6. Operating-Systems-Principles Operating-Systems-Principles Public

    Implement process scheduling, lock with priority inheritance, demand paging in XINU OS. All projects pass all tests

    C