Development Workflow

Workflow

To add a new module for the FPGA, a new verilog script is created in the pyrpl/fpga/rpl directory and its path added to the master TCL script.

The module can then be integrated into the red_pitaya_top.v file by connecting the respective wires to the new module. Afterwards, the build process has to be started manually and the new bitfile needs to be written to the FPGA.

When the bitfile is accepted by the FPGA, scoping can begin.

Example - basic FADS functionality

Goals:

• Use fast ADC to acquire external signal
• Switch pin on extension connector high if external signal is within set threshold

Implementation

Constraints

• Modify the constraints file such that a pin on the extension connector is driven directly instead of the standard differential signaling.
  • Check the schematics https://dl.dropboxusercontent.com/s/jkdy0p05a2vfcba/Red_Pitaya_Schematics_v1.0.1.pdf for the exact pin assignment on the FPGA. I chose to use the DIO1_P pin on the extension connector which is connected to pin H16 on the FPGA and driven using LVCMOS33 3.3 V signal. To be safe, I deactivated all other pins on the connector by making the other lines comments.

set_property IOSTANDARD LVCMOS33 [get_ports {DIO1_P}]
set_property SLEW       FAST     [get_ports {DIO1_P}]
set_property DRIVE      8        [get_ports {DIO1_P}]
set_property PACKAGE_PIN H16     [get_ports {DIO1_P}]

Scoping

• Use the scope to generate the external signal by (mis-)using the probe compensation 3V, 1 kHz square wave generator.
  • Connect the probe compensation port to the first channel on the scope with a T connector. Use the free end to connect to the RedPitaya directly. 1 kHz is still low enough to get away without 50 Ohm termination.
  • Connect the second channel of the scope to the DIO1_P with a 50 Ohm termination resistor directly in front of the scope.

FPGA code

We need a module that handles the logic (triggering output based on input). This is implemented in the red_pitaya_fads module. It takes a clock and the adc data vector (14 bit, signed) and provides a simple high/low signal as trigger output.

In this module, the thresholds are fixed to some experimentally derived parameters. The logic compares the adc data with the thresholds every clock cycle and sets the output to high if the adc data is within the thresholds.

module red_pitaya_fads #(
    parameter RSZ = 14, // RAM size: 2^RSZ,
    parameter signed low_threshold  = 14'b00000000001111,
    parameter signed high_threshold = 14'b00000011111111
)(
    // ADC
    input                   adc_clk_i       ,   // ADC clock
    input                   adc_rstn_i      ,   // ADC reset - active low
    input signed [14-1: 0]  adc_a_i         ,   // ADC data CHA

    output reg              sort_trig           // Sorting trigger
);

always @(posedge adc_clk_i) begin
    if ((adc_a_i > low_threshold) && (adc_a_i < high_threshold))
    begin
        sort_trig <= 1;
    end else begin
        sort_trig <= 0;
    end
end

endmodule

To be used, the red_pitaya_fads module has to be wired into the red_pitaya_top module.

red_pitaya_fads i_fads(
   .adc_clk_i      (   adc_clk                     ),
   .adc_rstn_i     (   adc_rstn                    ),
   .adc_a_i        (   to_scope_a                  ),
   .sort_trig      (   DIO1_P                      )
   );

This wires the adc_clk signal in the red_pitaya_top module to the adc_clk_i in the red_pitaya_fads module. It also wires the sort_trig signal of the red_pitaya_fads directly to the DIO1_P pin that we set in the constraints.