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  1. riscv-dv riscv-dv Public

    Forked from chipsalliance/riscv-dv

    SV/UVM based instruction generator for RISC-V processor verification

    SystemVerilog 1

  2. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

    SystemVerilog

  3. opentitan opentitan Public

    Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    SystemVerilog 1

  4. riscv-dbg riscv-dbg Public

    Forked from pulp-platform/riscv-dbg

    RISC-V Debug Support for our PULP RISC-V Cores

    SystemVerilog

  5. style-guides style-guides Public

    Forked from lowRISC/style-guides

    lowRISC Style Guides