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synopsys
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A small collection of tutorials and tools for ASIC design.
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May 16, 2017 - SystemVerilog
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
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May 12, 2024 - SystemVerilog
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