BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic
fpga
bdd
bdd-specs
rtl
verilog
systemverilog
uvm
verilog-hdl
bdd-framework
asic-verification
design-verification
asic-design
rtl-design
soc-design
soc-verification
uvm-verification
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Updated
Oct 1, 2024 - SystemVerilog