phoeniX RISC-V Processor
Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor
In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
This repository contains files regarding my CPU designs
Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
This is an implementation of a simple CPU in Logisim and Verilog.
The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.
This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.
Sample Verilog codes for digital circuits
Verilog CPU Design Project, ELEC 374 - Digital Systems Engineering
Verilog implementation of 16-bit RISC Processor with 4-stage pipeline
Single-cycle and multi-cycle implementation of a subset of MIPS instruction set
Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022