forked from YosysHQ/nextpnr
-
Notifications
You must be signed in to change notification settings - Fork 0
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
[pull] master from YosysHQ:master #258
Open
pull
wants to merge
1,325
commits into
timvideos:master
Choose a base branch
from
YosysHQ:master
base: master
Could not load branches
Branch not found: {{ refName }}
Loading
Could not load tags
Nothing to show
Loading
Are you sure you want to change the base?
Some commits from the old base branch may be removed from the timeline,
and old review comments may become outdated.
Open
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placednextpnr/fpga_interchange/globals.cc Lines 161 to 166 in 432b9d8
This comment was generated by todo based on a
|
substantial performance improvements are probably possible, although of questionable benefit givennextpnr/fpga_interchange/globals.cc Lines 200 to 205 in 432b9d8
This comment was generated by todo based on a
|
* Limited to Tangprimer 20k or GW2A-LV18PG256C8/I7 chip. * Clock lines are disabled. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Add description of BSRAM harness In some cases, Gowin IDE adds a number of LUTs and DFFs to the BSRAM. Here we are trying to add similar elements. More details with pictures: https://github.com/YosysHQ/apicula/blob/master/doc/bsram-fix.md Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
It seems that the internal registers on the BSRAM output pins in READ_MODE=1'b1 (pipeline) mode do not function properly because in the images generated by Gowin IDE an external register is added to each pin, and the BSRAM itself switches to READ_MODE=1'b0 (bypass) mode . This is observed on Tangnano9k and Tangnano20k boards. Here we repeat this fix. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
In the images generated by Gowin IDE, the signals for dynamic BSRAM block selection (BLKSEL[2:0]) are not always connected directly to the ports - some chips add LUT2, LUT3 or LUT4 to turn these signals into Clock Enable. Apparently there are chips with an error in the operation of these ports. Here we make such a decoder instead of using ports directly. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
As the board on the GW1N-1 chip becomes a rarity, its replacement is the Tangnano1k board with the GW1NZ-1 chip. This chip has a unique mechanism for turning off power to important things such as OSC, PLL, etc. Here we introduce a primitive that allows energy saving to be controlled dynamically. We also bring the names of some functions to uniformity. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
For pROM(X9) primitives in images generated by Gowin IDE, there is an interesting recommunication of inputs depending on the data bit depth. For example, in some cases, a high logical level may be applied to the Write Enable input, which, let’s say, is not entirely usual for Read Only memory. Here we will do similar manipulations. In addition, several minor bug fixes are included: - Fixed bit numbering for non-X9 series primitives. - Fixed decoder generation for BLKSEL - do not assume unused inputs are connected to GND. - Use default values for BSRAM parameters - don't assume their mandatory presence. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The statement in the Gowin documentation that in the reading mode "READ_MODE=0" the output register is not used and the OCE signal is ignored is not confirmed by practice - if the OCE was left unconnected or connected to the constant network, then a change in output data was observed even with CE=0, as well as the absence of such at CE=1. Synchronizing CE and OCE helps and the memory works properly in complex systems such as RISC-V emulation and i8080 emulation (with 32K RAM and 16K BSRAM based ROM), but there is no theoretical basis for this fix, so it is a hack. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
It was not taken into account that there are only 6 ALUs per cell. As a result, on complex designs where ALUs and LUT-based memory are involved and there are many LUTs (like in the RISCV emulator), there were sometimes false positives about placement conflicts. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
DQCE and DCS primitives are added. DQCE allows the internal logic to enable or disable the clock network in the quadrant. When clock network is disabled, all logic drivern by this clock is no longer toggled, thus reducing the total power consumtion of the device. DCS allows you to select one of four sources for two clock wires (6 and 7). Wires 6 and 7 have not been used up to this point. Since "hardware" primitives operate strictly in their own quadrants, user-specified primitives are converted into one or more "hardware" primitives as needed. Also: - minor edits to make the most of helper functions like connectPorts() - when creating bases, the corresponding constants are assigned to the VCC and GND wires, but for now huge nodes are used because, for an unknown reason, the constants mechanism makes large examples inoperable. So for now we remain on the nodes. Compatible with older Apicula databases. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
We filter out PIPs from these chips that bypass DCS. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2 * Himbaechel Gowin: Add support for CLKDIV and CLKDIV2 * Gowin Himbaechel: HCLK Bug fixes and corrections
* kernel: Add SDC file parser * kernel: Add sdc as valid option * kernel/sdc: Add error on EOF when fetching strings * kernel/sdc: WIP command parsing for set_false_path * kernel/sdc: Fully parse set_false_path * kernel/sdc: Handle review comments
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Implement the UserFlash primitive Some Gowin chips have embedded flash memory accessible from the fabric. Here we add primitives that allow access to this memory. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> * Gowin. Fix cell creation Signed-off-by: YRabbit <rabbit@yrabbit.cyou> --------- Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Some Clocks PIPS were not created due to a check for the presence of a delay class, now all wires are attributed to the class so that there is no longer any need for this check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Add DHCEN primitive. This primitive allows you to dynamically turn off and turn on the networks of high-speed clocks. This is done tracking the routes to the sinks and if the route passes through a special HCLK MUX (this may be the input MUX or the output MUX, as well as the interbank MUX), then the control signal of this MUX is used. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> * Gowin. Change the DHCEN binding Use the entire PIP instead of a wire - avoids normalisation and may also be useful in the future when calculating clock stuff. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> --------- Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Implement the EMCU primitive. Add support for the GW1NSR-4C's embedded Cortex-M3 processor. Since it uses flash in its own way, we disable additional flash processing for this case. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> * Gowin. Fix merge. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> --------- Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Fix truncation of output seed value from 64 bits to 32 bits (int instead of uint64) when written to json file. * Fix input seed value conversion when --seed option is used. * Remove input seed value scrambling (use of rngseed()) when --seed or --randomize-seed option is used since the output seed value will be the scrambled value and not the seed that was actually supplied or generated.
Signed-off-by: gatecat <gatecat@ds0.me>
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
See Commits and Changes for more details.
Created by pull[bot]
Can you help keep this open source service alive? 💖 Please sponsor : )