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Initial support for riscv32{e|em|emc}_unknown_none_elf #130555

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Initial support for riscv32{e|em|emc}_unknown_none_elf #130555

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22b8aca
Initial support for riscv32{e|em|emc}
hegza Sep 19, 2024
567c27a
Update to latest main
hegza Sep 19, 2024
7b8e249
doc: platform-support.md: Document port
hegza Sep 19, 2024
789ddc1
Work around the stage0 sanity check
hegza Sep 19, 2024
2d6cc54
Add assembly tests to satisfy 'tidy'
hegza Sep 19, 2024
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4 changes: 4 additions & 0 deletions compiler/rustc_target/src/spec/mod.rs
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Expand Up @@ -1802,6 +1802,10 @@ supported_targets! {
("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
("riscv32imafc-esp-espidf", riscv32imafc_esp_espidf),

("riscv32e-unknown-none-elf", riscv32e_unknown_none_elf),
("riscv32em-unknown-none-elf", riscv32em_unknown_none_elf),
("riscv32emc-unknown-none-elf", riscv32emc_unknown_none_elf),

("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
("riscv32imafc-unknown-none-elf", riscv32imafc_unknown_none_elf),
("riscv32imac-unknown-xous-elf", riscv32imac_unknown_xous_elf),
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30 changes: 30 additions & 0 deletions compiler/rustc_target/src/spec/targets/riscv32e_unknown_none_elf.rs
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@@ -0,0 +1,30 @@
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};

pub(crate) fn target() -> Target {
Target {
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
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We can either fix this to be correct for the RV32E targets...

llvm_target: "riscv32".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Bare RISC-V (RV32E ISA)".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
pointer_width: 32,
arch: "riscv32".into(),

options: TargetOptions {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
atomic_cas: false,
features: "+e,+forced-atomics".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}
30 changes: 30 additions & 0 deletions compiler/rustc_target/src/spec/targets/riscv32em_unknown_none_elf.rs
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@@ -0,0 +1,30 @@
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};

pub(crate) fn target() -> Target {
Target {
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
llvm_target: "riscv32".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Bare RISC-V (RV32EM ISA)".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
pointer_width: 32,
arch: "riscv32".into(),

options: TargetOptions {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
atomic_cas: false,
features: "+e,+m,+forced-atomics".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}
30 changes: 30 additions & 0 deletions compiler/rustc_target/src/spec/targets/riscv32emc_unknown_none_elf.rs
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@@ -0,0 +1,30 @@
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};

pub(crate) fn target() -> Target {
Target {
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
llvm_target: "riscv32".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Bare RISC-V (RV32EMC ISA)".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
pointer_width: 32,
arch: "riscv32".into(),

options: TargetOptions {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
atomic_cas: false,
features: "+e,+m,+c,+forced-atomics".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}
3 changes: 3 additions & 0 deletions src/bootstrap/src/core/sanity.rs
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Expand Up @@ -37,6 +37,9 @@ pub struct Finder {
const STAGE0_MISSING_TARGETS: &[&str] = &[
// just a dummy comment so the list doesn't get onelined
"armv7-rtems-eabihf",
"riscv32e-unknown-none-elf",
"riscv32em-unknown-none-elf",
"riscv32emc-unknown-none-elf",
];

/// Minimum version threshold for libstdc++ required when using prebuilt LLVM
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3 changes: 3 additions & 0 deletions src/doc/rustc/src/platform-support.md
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Expand Up @@ -410,5 +410,8 @@ target | std | host | notes
[`riscv32imafc-unknown-nuttx-elf`](platform-support/nuttx.md) | * | | RISC-V 32bit with NuttX
[`riscv64imac-unknown-nuttx-elf`](platform-support/nuttx.md) | * | | RISC-V 64bit with NuttX
[`riscv64gc-unknown-nuttx-elf`](platform-support/nuttx.md) | * | | RISC-V 64bit with NuttX
[`riscv32e-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32E ISA)
[`riscv32em-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32EM ISA)
[`riscv32emc-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32EMC ISA)

[runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets
4 changes: 2 additions & 2 deletions src/doc/rustc/src/platform-support/riscv32-unknown-none-elf.md
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@@ -1,12 +1,12 @@
# `riscv32{i,im,ima,imc,imac,imafc}-unknown-none-elf`
# `riscv32{i,im,ima,imc,imac,imafc,e,em,emc}-unknown-none-elf`

**Tier: 2**

Bare-metal target for RISC-V CPUs with the RV32I, RV32IM, RV32IMC, RV32IMAFC and RV32IMAC ISAs.

**Tier: 3**

Bare-metal target for RISC-V CPUs with the RV32IMA ISA.
Bare-metal target for RISC-V CPUs with the RV32IMA, RV32E, RV32EM and RV32EMC ISAs.

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Or we can add documentation that we don't actually generate code with a 4-byte stack alignment, but rather to a 16-byte stack alignment, which is I guess technically acceptable even if it is incorrect.

## Target maintainers

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Did the RISC-V team agree to provide maintenance for the RV32E* targets?

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Oops, I did not mean to imply that 🙂 I'll remove the mention from this file.

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9 changes: 9 additions & 0 deletions tests/assembly/targets/targets-elf.rs
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Expand Up @@ -441,6 +441,15 @@
//@ revisions: riscv64imac_unknown_none_elf
//@ [riscv64imac_unknown_none_elf] compile-flags: --target riscv64imac-unknown-none-elf
//@ [riscv64imac_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: riscv32e_unknown_none_elf
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It might be a good idea to move these new comments above so that the list is ordered.

//@ [riscv32e_unknown_none_elf] compile-flags: --target riscv32e-unknown-none-elf
//@ [riscv32e_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: riscv32em_unknown_none_elf
//@ [riscv32em_unknown_none_elf] compile-flags: --target riscv32em-unknown-none-elf
//@ [riscv32em_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: riscv32emc_unknown_none_elf
//@ [riscv32emc_unknown_none_elf] compile-flags: --target riscv32emc-unknown-none-elf
//@ [riscv32emc_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: s390x_unknown_linux_gnu
//@ [s390x_unknown_linux_gnu] compile-flags: --target s390x-unknown-linux-gnu
//@ [s390x_unknown_linux_gnu] needs-llvm-components: systemz
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