Add optional backend for critical-section
#191
Conversation
This is similar to the single-threaded bare metal implementations in `cortex-m` and `riscv`. In theory there could be a race condition in `acquire` if an interrupt occurs between the `read` and `write`, and the interrupt disables `IME`. But it's probably not sensible to have an interrupt disable interrupts, so I don't think it's necessarily to complicate things with inline assembly using `swp`.
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I don't object to this, but I also have never heard of this crate before. I guess this is just a commonly used utility crate? Interrupts actually happen with interrupts disabled (in the program status register) by default, and then our asm interrupt handler re-enabled interrupts as part of switching to System mode for the Rust interrupt handler to run. I coulda sworn we had a utility fn to cleanly do a |
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Yeah, it seems to be commonly provided by basically all the hal crates (or one of their dependencies, anyway). It sounds useful for creating portable abstractions, and in particular I see embassy-executor and embassy-time seem to use it, so presumably a backend like this would be needed to use those with Looking at |
This is similar to the single-threaded bare metal implementations in
cortex-mandriscv.In theory there could be a race condition in
acquireif an interrupt occurs between thereadandwrite, and the interrupt disablesIME. But it's probably not sensible to have an interrupt disable interrupts, so I don't think it's necessarily to complicate things with inline assembly usingswp.