Update/sdk1.4.2

arch/riscv/cpu/c9xx/Makefile

@@ -6,3 +6,4 @@
 
 obj-y += dram.o
 obj-y += cpu.o
+obj-y += feature.o

arch/riscv/cpu/c9xx/feature.c

@@ -0,0 +1,114 @@
+#include <common.h>
+#include <asm/types.h>
+#include <asm/asm.h>
+#include <asm/csr.h>
+
+void setup_features(void)
+{
+	unsigned int i, cpu_type, cpu_ver;
+	unsigned long version[8];
+
+	for (i = 0; i < 8; i++)
+		version[i] = csr_read(CSR_MCPUID);
+
+	cpu_type = (version[0] >> 18) & 0xf;
+	cpu_ver  = (version[1] >> 12) & 0xffff;
+
+	/*
+	 * Warning: CSR_MCCR2 contains an L2 cache latency setting,
+	 * you need to confirm it by your own soc design.
+	 */
+	switch (cpu_type) {
+	case 0x3:
+		if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x
+			csr_write(CSR_MCCR2, 0xe0010009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x6e30c);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver == 0x10ca) { //1.3.10
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x66e30c);
+			csr_write(CSR_MHCR, 0x17f);
+			csr_write(CSR_MHINT2, 0x420000);
+			csr_write(CSR_MHINT4, 0x410);
+		} else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x16e30c);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0xe6e30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x1ee30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x1ee30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x438000);
+			csr_write(CSR_MHINT, 0x31ea32c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x4:
+		if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) {
+			csr_write(CSR_MHCR, 0x17f);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x650c);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x5:
+		if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe0420008);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x2c50c);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else if (cpu_ver >= 0x0040 && cpu_ver <= 0xffff) { //0.1.0~
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xa042000a);
+			csr_write(CSR_MXSTATUS, 0x438000);
+			csr_write(CSR_MHINT, 0x21aa10c);
+			csr_write(CSR_MHCR, 0x10011ff);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x6:
+		if (cpu_ver >= 0x0) {
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xA042000A);
+			csr_write(CSR_MXSTATUS, 0x638001);
+			csr_write(CSR_MHINT, 0x3A1AA10C);
+			csr_write(CSR_MHCR, 0x10011BF);
+		} else {
+			while(1);
+		}
+		break;
+	default:
+		while(1);
+	}
+}

arch/riscv/cpu/mtrap.S

@@ -104,3 +104,45 @@ trap_entry:
 	LREG x2,   2 * REGBYTES(sp)
 	addi sp, sp, 32 * REGBYTES
 	MODE_PREFIX(ret)
+
+	/* trap secondary_entry */
+	.align 10
+	.global secondary_entry
+secondary_entry:
+	/*
+	 * Clear L1 cache & BTB & BHT ...
+	 */
+	li      t0, 0x70013
+	csrw    CSR_MCOR, t0
+
+	/*
+	 * Enable cache coherency
+	 */
+	li	t0, 1
+	csrw	CSR_MSMPR, t0
+
+	/*
+	 *Prepare percpu stack
+	 */
+	csrr	t0, mhartid
+	li	t1, 0x100
+	mul	t1, t1, t0
+	lla	sp, stacks
+	add	sp, sp, t1
+
+	/*
+	 * Call C routine
+	 */
+	call	setup_features
+	call	next_stage
+
+	/*
+	 * Never get here, dead loop
+	 */
+	j .
+
+	.align 10
+stacks:
+	.rept 0x1000
+	.long
+	.endr

arch/riscv/dts/light-a-val.dts

@@ -306,8 +306,8 @@
 			spi-max-frequency = <100000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			flash@0 {
-				compatible = "jedec,spi-nor";
+			tpm@0{
+				compatible = "z32h330tc,z32h330tc-spi";
 				reg = <0>;
 				spi-max-frequency = <40000000>;
 			};

arch/riscv/include/asm/arch-thead/boot_mode.h

@@ -34,7 +34,9 @@ typedef enum image_type {
 	T_ROOTFS = 4,
 	T_TF = 2,
 	T_TEE = 5,
-	T_UBOOT = 6
+	T_UBOOT = 6,
+	T_USER = 7,
+	T_SBMETA = 8,
 } img_type_t;
 
 static const char header_magic[4] = {'T', 'H', 'E', 'D'};

arch/riscv/include/asm/arch-thead/light-reset.h

@@ -0,0 +1,17 @@
+#ifndef __LIGHT_RESET_H__
+#define __LIGHT_RESET_H__
+
+#define APSYS_RSTGEN_BASE	0xFFEF014000
+#define REG_C910_SWRST		(APSYS_RSTGEN_BASE + 0x4)
+#define APSYS_REG_BASE		0xFFEF018000
+#define REG_C910_CORE0_RVBA_L	(APSYS_REG_BASE + 0x50)
+#define REG_C910_CORE0_RVBA_H	(APSYS_REG_BASE + 0x54)
+#define REG_C910_CORE1_RVBA_L	(APSYS_REG_BASE + 0x58)
+#define REG_C910_CORE1_RVBA_H	(APSYS_REG_BASE + 0x5C)
+#define REG_C910_CORE2_RVBA_L	(APSYS_REG_BASE + 0x60)
+#define REG_C910_CORE2_RVBA_H	(APSYS_REG_BASE + 0x64)
+#define REG_C910_CORE3_RVBA_L	(APSYS_REG_BASE + 0x68)
+#define REG_C910_CORE3_RVBA_H	(APSYS_REG_BASE + 0x6C)
+#define REG_PLIC_DELEGATE	0xffd81ffffc
+
+#endif /* __LIGHT_RESET_H__ */

arch/riscv/include/asm/atomic.h

@@ -0,0 +1,53 @@
+#ifndef _ASM_RISCV_ATOMIC_H
+#define _ASM_RISCV_ATOMIC_H
+
+#include <linux/types.h>
+#include <asm/barrier.h>
+
+typedef struct {
+	volatile long counter;
+} atomic_t;
+
+#define ATOMIC_INIT(_lptr, val) (_lptr)->counter = (val)
+
+#define ATOMIC_INITIALIZER(val)   \
+	{                         \
+		.counter = (val), \
+	}
+
+long atomic_read(atomic_t *atom)
+{
+	long ret = atom->counter;
+	rmb();
+	return ret;
+}
+
+void atomic_write(atomic_t *atom, long value)
+{
+	atom->counter = value;
+	wmb();
+}
+
+long atomic_add_return(atomic_t *atom, long value)
+{
+	long ret;
+#if __SIZEOF_LONG__ == 4
+	__asm__ __volatile__("	amoadd.w.aqrl  %1, %2, %0"
+			     : "+A"(atom->counter), "=r"(ret)
+			     : "r"(value)
+			     : "memory");
+#elif __SIZEOF_LONG__ == 8
+	__asm__ __volatile__("	amoadd.d.aqrl  %1, %2, %0"
+			     : "+A"(atom->counter), "=r"(ret)
+			     : "r"(value)
+			     : "memory");
+#endif
+	return ret + value;
+}
+
+long atomic_sub_return(atomic_t *atom, long value)
+{
+	return atomic_add_return(atom, -value);
+}
+
+#endif /* _ASM_RISCV_ATOMIC_H */

arch/riscv/include/asm/csr.h

@@ -104,15 +104,23 @@
 #define CSR_CYCLEH		0xc80
 #define CSR_TIMEH		0xc81
 #define CSR_INSTRETH		0xc82
+#define CSR_MVENDORID		0xf11
+#define CSR_MARCHID		0xf12
+#define CSR_MIMPID		0xf13
 #define CSR_MHARTID		0xf14
+#define CSR_MCPUID		0xfc0
 
-#define CSR_SMPEN			0x7f3
-#define CSR_MTEE			0x7f4
+#define CSR_SMPEN        0x7f3
+#define CSR_MTEE         0x7f4
 #define CSR_MCOR         0x7c2
 #define CSR_MHCR         0x7c1
 #define CSR_MCCR2        0x7c3
 #define CSR_MHINT        0x7c5
+#define CSR_MHINT2       0x7cc
+#define CSR_MHINT3       0x7cd
+#define CSR_MHINT4       0x7ce
 #define CSR_MXSTATUS     0x7c0
+#define CSR_MSMPR        0x7f3
 #define CSR_PLIC_BASE    0xfc1
 
 #define sync_is()   asm volatile (".long 0x01b0000b")