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[LLVM][XTHeadVector] Implement intrinsics for vsll/vsrl/vsra. (llvm#55)
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* [LLVM][XTHeadVector] Define pseudos for vsll/vsrl/vsra.

* [LLVM][XTHeadVector] Define intrinsics for vsll/vsrl/vsra.

* [LLVM][XTHeadVector] Define pseudos and pats.

* [LLVM][XTHeadVector] Add test cases.

* [LLVM][NFC] Update README.
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AinsleySnow authored and RevySR committed Apr 3, 2024
1 parent 80fa688 commit db491ac
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4 changes: 4 additions & 0 deletions README.md
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Expand Up @@ -39,6 +39,10 @@ Any feature not listed below but present in the specification should be consider
- (Done) `vand.{vv,vx,vi}`
- (Done) `vor.{vv,vx,vi}`
- (Done) `vxor.{vv,vx,vi}`
- (Done) `12.5. Vector Single-Width Bit Shift Instructions`
- (Done) `vsll.{vv,vx,vi}`
- (Done) `vsrl.{vv,vx,vi}`
- (Done) `vsra.{vv,vx,vi}`
- (WIP) Clang intrinsics related to the `XTHeadVector` extension:
- (WIP) `6. Configuration-Setting and Utility`
- (Done) `6.1. Set vl and vtype`
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22 changes: 22 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
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Expand Up @@ -586,6 +586,18 @@ let TargetPrefix = "riscv" in {
let VLOperand = 4;
}

// For destination vector type is the same as
// first source vector (with mask but no policy).
// The second source operand must match the destination type or be an XLen scalar.
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
class XVBinaryAAShiftMasked
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 4;
}

multiclass XVBinaryAAX {
def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked;
def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked;
Expand All @@ -595,6 +607,11 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RISCVBinaryABXUnMasked;
def "int_riscv_" # NAME # "_mask" : XVBinaryABXMasked;
}

multiclass XVBinaryAAShift {
def "int_riscv_" # NAME : RISCVBinaryAAShiftUnMasked;
def "int_riscv_" # NAME # "_mask" : XVBinaryAAShiftMasked;
}
}

let TargetPrefix = "riscv" in {
Expand Down Expand Up @@ -624,6 +641,11 @@ let TargetPrefix = "riscv" in {
defm th_vand : XVBinaryAAX;
defm th_vor : XVBinaryAAX;
defm th_vxor : XVBinaryAAX;

// 12.5. Vector Single-Width Bit Shift Instructions
defm th_vsll : XVBinaryAAShift;
defm th_vsrl : XVBinaryAAShift;
defm th_vsra : XVBinaryAAShift;
} // TargetPrefix = "riscv"

let TargetPrefix = "riscv" in {
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60 changes: 60 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td
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Expand Up @@ -1789,6 +1789,24 @@ multiclass XVPseudoVCALUM_VM_XM<string Constraint> {
}
}

multiclass XVPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxListXTHeadV in {
defvar mx = m.MX;
defvar WriteVShiftV_MX = !cast<SchedWrite>("WriteVShiftV_" # mx);
defvar WriteVShiftX_MX = !cast<SchedWrite>("WriteVShiftX_" # mx);
defvar WriteVShiftI_MX = !cast<SchedWrite>("WriteVShiftI_" # mx);
defvar ReadVShiftV_MX = !cast<SchedRead>("ReadVShiftV_" # mx);
defvar ReadVShiftX_MX = !cast<SchedRead>("ReadVShiftX_" # mx);

defm "" : XVPseudoBinaryV_VV<m, Constraint>,
Sched<[WriteVShiftV_MX, ReadVShiftV_MX, ReadVShiftV_MX, ReadVMask]>;
defm "" : XVPseudoBinaryV_VX<m, Constraint>,
Sched<[WriteVShiftX_MX, ReadVShiftV_MX, ReadVShiftX_MX, ReadVMask]>;
defm "" : XVPseudoBinaryV_VI<ImmType, m, Constraint>,
Sched<[WriteVShiftI_MX, ReadVShiftV_MX, ReadVMask]>;
}
}

//===----------------------------------------------------------------------===//
// Helpers to define the intrinsic patterns for the XTHeadVector extension.
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -2207,6 +2225,48 @@ let Predicates = [HasVendorXTHeadV] in {
defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vxor", "PseudoTH_VXOR", AllIntegerXVectors>;
}

//===----------------------------------------------------------------------===//
// 12.5. Vector Single-Width Bit Shift Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasVendorXTHeadV] in {
defm PseudoTH_VSLL : XVPseudoVSHT_VV_VX_VI<uimm5>;
defm PseudoTH_VSRL : XVPseudoVSHT_VV_VX_VI<uimm5>;
defm PseudoTH_VSRA : XVPseudoVSHT_VV_VX_VI<uimm5>;
} // Predicates = [HasVendorXTHeadV]

let Predicates = [HasVendorXTHeadV] in {
defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vsll", "PseudoTH_VSLL", AllIntegerXVectors,
uimm5>;
defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vsrl", "PseudoTH_VSRL", AllIntegerXVectors,
uimm5>;
defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vsra", "PseudoTH_VSRA", AllIntegerXVectors,
uimm5>;

foreach vti = AllIntegerXVectors in {
// Emit shift by 1 as an add since it might be faster.
let Predicates = GetXVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (int_riscv_th_vsll (vti.Vector undef),
(vti.Vector vti.RegClass:$rs1),
(XLenVT 1), VLOpFrag)),
(!cast<Instruction>("PseudoTH_VADD_VV_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (int_riscv_th_vsll_mask (vti.Vector vti.RegClass:$merge),
(vti.Vector vti.RegClass:$rs1),
(XLenVT 1),
(vti.Mask V0),
VLOpFrag)),
(!cast<Instruction>("PseudoTH_VADD_VV_"#vti.LMul.MX#"_MASK")
vti.RegClass:$merge,
vti.RegClass:$rs1,
vti.RegClass:$rs1,
(vti.Mask V0),
GPR:$vl,
vti.Log2SEW)>;
}
}
} // Predicates = [HasVendorXTHeadV]

//===----------------------------------------------------------------------===//
// 12.14. Vector Integer Merge and Move Instructions
//===----------------------------------------------------------------------===//
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