[hardware] Fix performance bug in Snitch decoder

This fixes a performance bug in the Snitch decoder: instructions that do not use the destination register get `uses_rd` asserted by default. The 11:7 instruction field is also always assigned to the destination address. If this field corresponds to a register in the scoreboard, the instruction causes a stall.
pulp-platform · Sep 23, 2024 · 0681b42 · 0681b42
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commit 0681b42
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -41,6 +41,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Properly disable the debugging CSRs in ASIC implementations
 - Fix a bug in the  DMA's distributed midend
 - Fix bugs in radix2, radix4by2 parallelization and loading of data for radix4 CFFT
+- Fix performance bug in Snitch decoder
 
 ## 0.6.0 - 2023-01-09
 

diff --git a/hardware/deps/snitch/src/snitch.sv b/hardware/deps/snitch/src/snitch.sv
@@ -501,61 +501,70 @@ module snitch
       riscv_instr::BEQ: begin
         is_branch = 1'b1;
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         alu_op = Eq;
         opa_select = Reg;
         opb_select = Reg;
       end
       riscv_instr::BNE: begin
         is_branch = 1'b1;
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         alu_op = Neq;
         opa_select = Reg;
         opb_select = Reg;
       end
       riscv_instr::BLT: begin
         is_branch = 1'b1;
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         alu_op = Slt;
         opa_select = Reg;
         opb_select = Reg;
       end
       riscv_instr::BLTU: begin
         is_branch = 1'b1;
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         alu_op = Sltu;
         opa_select = Reg;
         opb_select = Reg;
       end
       riscv_instr::BGE: begin
         is_branch = 1'b1;
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         alu_op = Ge;
         opa_select = Reg;
         opb_select = Reg;
       end
       riscv_instr::BGEU: begin
         is_branch = 1'b1;
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         alu_op = Geu;
         opa_select = Reg;
         opb_select = Reg;
       end
       // Load/Stores
       riscv_instr::SB: begin
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         is_store = 1'b1;
         opa_select = Reg;
         opb_select = SImmediate;
       end
       riscv_instr::SH: begin
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         is_store = 1'b1;
         ls_size = HalfWord;
         opa_select = Reg;
         opb_select = SImmediate;
       end
       riscv_instr::SW: begin
         write_rd = 1'b0;
+        uses_rd = 1'b0;
         is_store = 1'b1;
         ls_size = Word;
         opa_select = Reg;
@@ -664,6 +673,7 @@ module snitch
       riscv_instr::EBREAK: begin
         // TODO(zarubaf): Trap to precise address
         write_rd = 1'b0;
+        uses_rd = 1'b0;
       end
       // NOP Instructions
       riscv_instr::FENCE: begin
@@ -1595,6 +1605,7 @@ module snitch
       riscv_instr::P_SB_IRPOST: begin  // Xpulpimg: p.sb rs2,simm(rs1!)
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b0;
           write_rs1 = 1'b1;
           is_store = 1'b1;
           is_postincr = 1'b1;
@@ -1608,6 +1619,7 @@ module snitch
       riscv_instr::P_SH_IRPOST: begin  // Xpulpimg: p.sh
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b0;
           write_rs1 = 1'b1;
           is_store = 1'b1;
           is_postincr = 1'b1;
@@ -1622,6 +1634,7 @@ module snitch
       riscv_instr::P_SW_IRPOST: begin  // Xpulpimg: p.sw
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b0;
           write_rs1 = 1'b1;
           is_store = 1'b1;
           is_postincr = 1'b1;
@@ -1640,6 +1653,7 @@ module snitch
       riscv_instr::P_SB_RRPOST: begin  // Xpulpimg: p.sb rs2,rs3(rs1!)
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b1;
           write_rs1 = 1'b1;
           is_store = 1'b1;
           is_postincr = 1'b1;
@@ -1654,6 +1668,7 @@ module snitch
       riscv_instr::P_SH_RRPOST: begin  // Xpulpimg: p.sh
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b1;
           write_rs1 = 1'b1;
           is_store = 1'b1;
           is_postincr = 1'b1;
@@ -1669,6 +1684,7 @@ module snitch
       riscv_instr::P_SW_RRPOST: begin  // Xpulpimg: p.sw
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b1;
           write_rs1 = 1'b1;
           is_store = 1'b1;
           is_postincr = 1'b1;
@@ -1684,6 +1700,7 @@ module snitch
       riscv_instr::P_SB_RR: begin      // Xpulpimg: p.sb rs2,rs3(rs1)
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b1;
           is_store = 1'b1;
           opa_select = Reg;
           opb_select = RegRd;
@@ -1696,6 +1713,7 @@ module snitch
       riscv_instr::P_SH_RR: begin      // Xpulpimg: p.sh
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b1;
           is_store = 1'b1;
           ls_size = HalfWord;
           opa_select = Reg;
@@ -1709,6 +1727,7 @@ module snitch
       riscv_instr::P_SW_RR: begin      // Xpulpimg: p.sw
         if (snitch_pkg::XPULPIMG) begin
           write_rd = 1'b0;
+          uses_rd = 1'b1;
           is_store = 1'b1;
           ls_size = Word;
           opa_select = Reg;
@@ -1724,6 +1743,7 @@ module snitch
         if (snitch_pkg::XPULPIMG) begin
           is_branch = 1'b1;
           write_rd = 1'b0;
+          uses_rd = 1'b0;
           alu_op = Eq;
           opa_select = Reg;
           opb_select = PBImmediate;
@@ -1736,6 +1756,7 @@ module snitch
         if (snitch_pkg::XPULPIMG) begin
           is_branch = 1'b1;
           write_rd = 1'b0;
+          uses_rd = 1'b0;
           alu_op = Neq;
           opa_select = Reg;
           opb_select = PBImmediate;