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    18 repositories

    • osstoolchain-docker-things

      Public
      Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more
      Makefile
      •1•10•1•0•Updated Oct 2, 2024Oct 2, 2024

    • caas-wizard

      Public
      The core of the CaaS platform, configuration parser and Makefile generator
      Python
      •
      GNU General Public License v3.0
      •0•0•2•0•Updated Oct 2, 2024Oct 2, 2024

    • user-examples

      Public
      User examples for the official and unofficial FPGAOL platforms
      Verilog
      •0•1•0•0•Updated Aug 29, 2024Aug 29, 2024

    • fpgaol-caas-backend

      Public
      Compiling as a Service backend.
      Python
      •
      MIT License
      •2•1•0•0•Updated Aug 7, 2024Aug 7, 2024

    • openFPGALoader

      Public
      Universal utility for programming FPGA
      C++
      •
      Apache License 2.0
      •252•0•0•0•Updated Jul 13, 2024Jul 13, 2024

    • demo-projects

      Public
      Demo projects for various Kintex FPGA boards
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •15•1•0•0•Updated Jun 12, 2024Jun 12, 2024

    • cocotb-fifo-test

      Public
      SystemVerilog
      •0•1•0•0•Updated May 5, 2024May 5, 2024

    • new_fpgaol

      Public
      new fpgaol platform with CodeEdit, Compiling and Program
      Vue
      •
      MIT License
      •1•0•0•0•Updated Apr 17, 2024Apr 17, 2024

    • ss_blast

      Public
      Loading bitstream via Slave SelectMAP 32-bit via ZYNQ AXI GPIO
      C
      •0•3•0•0•Updated Apr 13, 2024Apr 13, 2024

    • core_jpeg

      Public
      High throughput JPEG decoder in Verilog for FPGA
      Verilog
      •
      Apache License 2.0
      •42•0•0•0•Updated Mar 12, 2024Mar 12, 2024

    • zynq-mkbootimage

      Public
      An open source replacement of the Xilinx bootgen application.
      C
      •
      BSD 2-Clause "Simplified" License
      •49•0•0•0•Updated Feb 26, 2024Feb 26, 2024

    • openXC7-TetriSaraj

      Public
      Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
      Verilog
      •1•0•0•0•Updated Feb 22, 2024Feb 22, 2024

    • gray_decoder-FPGAOL_CAAS_test

      Public
      Academic project to test the https://caas.symbioticeda.com/ platform.
      Verilog
      •1•0•0•0•Updated Feb 17, 2024Feb 17, 2024

    • fpgaol-caas-frontend

      Public
      Vue
      •0•3•0•0•Updated Feb 16, 2024Feb 16, 2024

    • FPGAOL-Caas-Tangnano9k-Test

      Public
      Verilog
      •1•0•0•0•Updated Feb 8, 2024Feb 8, 2024

    • picorv32-caas

      Public
      Verilog
      •0•0•0•0•Updated Nov 14, 2023Nov 14, 2023

    • eccen-guard

      Public
      The name is just cool... Might be something later
      GNU General Public License v3.0
      •0•0•0•0•Updated Apr 23, 2023Apr 23, 2023

    • toolchain-installer

      Public
      Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
      Shell
      •
      BSD 3-Clause "New" or "Revised" License
      •5•0•0•0•Updated Mar 31, 2023Mar 31, 2023