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Code clean-up of the number of register address bits #2483

Merged
merged 2 commits into from
Aug 30, 2024
Merged

Code clean-up of the number of register address bits #2483

merged 2 commits into from
Aug 30, 2024

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JeanRochCoulon
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@JeanRochCoulon JeanRochCoulon commented Aug 30, 2024 •
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rs1[4:0], rs2[4:0], rd[4:0] are replaced by rs1, rs2 and rd.

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core/decoder.sv Outdated
Comment on lines 1410 to 1413
instruction_o.fu = ALU;
imm_select = UIMM;
instruction_o.use_pc = 1'b1;
instruction_o.rd[4:0] = instr.utype.rd;
instruction_o.rd = instr.utype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.fu = ALU;
imm_select = UIMM;
instruction_o.use_pc = 1'b1;
instruction_o.rd[4:0] = instr.utype.rd;
instruction_o.rd = instr.utype.rd;
instruction_o.fu = ALU;
imm_select = UIMM;
instruction_o.use_pc = 1'b1;
instruction_o.rd = instr.utype.rd;

core/decoder.sv Outdated Show resolved Hide resolved
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core/decoder.sv Outdated
Comment on lines 475 to 476
check_fprm = 1'b1;
allow_replication = 1'b1;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
check_fprm = 1'b1;
allow_replication = 1'b1;
check_fprm = 1'b1;
allow_replication = 1'b1;

core/decoder.sv Outdated
Comment on lines 480 to 481
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0

core/decoder.sv Outdated
check_fprm = 1'b1;
allow_replication = 1'b1;
// decode vectorial FP instruction
unique case (instr.rvftype.vecfltop)
5'b00001: begin
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0
instruction_o.rs2[4:0] = instr.rvftype.rs1; // Operand B is set to rs1
instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1
imm_select = IIMM; // Operand C is set to rs2
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
imm_select = IIMM; // Operand C is set to rs2
imm_select = IIMM; // Operand C is set to rs2

core/decoder.sv Outdated
@@ -820,9 +820,9 @@
// --------------------------
riscv::OpcodeOp32: begin
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;

core/decoder.sv Outdated
@@ -1391,9 +1391,9 @@
riscv::OpcodeJalr: begin
instruction_o.fu = CTRL_FLOW;
instruction_o.op = ariane_pkg::JALR;
instruction_o.rs1[4:0] = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rs1 = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;

core/decoder.sv Outdated
imm_select = IIMM;
instruction_o.rd[4:0] = instr.itype.rd;
instruction_o.rd = instr.itype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.itype.rd;
instruction_o.rd = instr.itype.rd;

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core/decoder.sv Outdated
Comment on lines 480 to 481
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0

core/decoder.sv Outdated
// decode vectorial FP instruction
unique case (instr.rvftype.vecfltop)
5'b00001: begin
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0
instruction_o.rs2[4:0] = instr.rvftype.rs1; // Operand B is set to rs1
instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1
imm_select = IIMM; // Operand C is set to rs2
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
imm_select = IIMM; // Operand C is set to rs2
imm_select = IIMM; // Operand C is set to rs2

core/decoder.sv Outdated
@@ -820,9 +820,9 @@ module decoder
// --------------------------
riscv::OpcodeOp32: begin
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;

core/decoder.sv Outdated
@@ -1391,9 +1391,9 @@ module decoder
riscv::OpcodeJalr: begin
instruction_o.fu = CTRL_FLOW;
instruction_o.op = ariane_pkg::JALR;
instruction_o.rs1[4:0] = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rs1 = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;

core/decoder.sv Outdated
imm_select = IIMM;
instruction_o.rd[4:0] = instr.itype.rd;
instruction_o.rd = instr.itype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.itype.rd;
instruction_o.rd = instr.itype.rd;

core/decoder.sv Outdated
@@ -1402,21 +1402,21 @@ module decoder
riscv::OpcodeJal: begin
instruction_o.fu = CTRL_FLOW;
imm_select = JIMM;
instruction_o.rd[4:0] = instr.utype.rd;
instruction_o.rd = instr.utype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.utype.rd;
instruction_o.rd = instr.utype.rd;

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github-actions bot reviewed Aug 30, 2024
View reviewed changes
core/decoder.sv Outdated
instruction_o.rs2[4:0] = instr.rvftype.rs1; // Operand B is set to rs1
instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition
instruction_o.rs1 = '0; // Operand A is set to 0
instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1
imm_select = IIMM; // Operand C is set to rs2
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
imm_select = IIMM; // Operand C is set to rs2
imm_select = IIMM; // Operand C is set to rs2

core/decoder.sv Outdated
@@ -820,9 +820,9 @@
// --------------------------
riscv::OpcodeOp32: begin
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;

core/decoder.sv Outdated
@@ -1391,9 +1391,9 @@
riscv::OpcodeJalr: begin
instruction_o.fu = CTRL_FLOW;
instruction_o.op = ariane_pkg::JALR;
instruction_o.rs1[4:0] = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rs1 = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;

core/decoder.sv Outdated
imm_select = IIMM;
instruction_o.rd[4:0] = instr.itype.rd;
instruction_o.rd = instr.itype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.itype.rd;
instruction_o.rd = instr.itype.rd;

core/decoder.sv Outdated
@@ -1402,21 +1402,21 @@
riscv::OpcodeJal: begin
instruction_o.fu = CTRL_FLOW;
imm_select = JIMM;
instruction_o.rd[4:0] = instr.utype.rd;
instruction_o.rd = instr.utype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.utype.rd;
instruction_o.rd = instr.utype.rd;

github-actions[bot]
github-actions bot reviewed Aug 30, 2024
View reviewed changes
core/decoder.sv Outdated
@@ -820,9 +820,9 @@ module decoder
// --------------------------
riscv::OpcodeOp32: begin
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;

core/decoder.sv Outdated
@@ -1391,9 +1391,9 @@ module decoder
riscv::OpcodeJalr: begin
instruction_o.fu = CTRL_FLOW;
instruction_o.op = ariane_pkg::JALR;
instruction_o.rs1[4:0] = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rs1 = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;

core/decoder.sv Outdated
imm_select = IIMM;
instruction_o.rd[4:0] = instr.itype.rd;
instruction_o.rd = instr.itype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.itype.rd;
instruction_o.rd = instr.itype.rd;

core/decoder.sv Outdated
@@ -1402,21 +1402,21 @@ module decoder
riscv::OpcodeJal: begin
instruction_o.fu = CTRL_FLOW;
imm_select = JIMM;
instruction_o.rd[4:0] = instr.utype.rd;
instruction_o.rd = instr.utype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.utype.rd;
instruction_o.rd = instr.utype.rd;

core/decoder.sv Outdated
Comment on lines 1417 to 1418
imm_select = UIMM;
instruction_o.fu = ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
imm_select = UIMM;
instruction_o.fu = ALU;
imm_select = UIMM;
instruction_o.fu = ALU;

github-actions[bot]
github-actions bot reviewed Aug 30, 2024
View reviewed changes
core/decoder.sv Outdated
imm_select = IIMM;
instruction_o.rd[4:0] = instr.itype.rd;
instruction_o.rd = instr.itype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.itype.rd;
instruction_o.rd = instr.itype.rd;

core/decoder.sv Outdated
@@ -1402,21 +1402,21 @@ module decoder
riscv::OpcodeJal: begin
instruction_o.fu = CTRL_FLOW;
imm_select = JIMM;
instruction_o.rd[4:0] = instr.utype.rd;
instruction_o.rd = instr.utype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.utype.rd;
instruction_o.rd = instr.utype.rd;

core/decoder.sv Outdated
Comment on lines 1417 to 1418
imm_select = UIMM;
instruction_o.fu = ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
imm_select = UIMM;
instruction_o.fu = ALU;
imm_select = UIMM;
instruction_o.fu = ALU;

github-actions[bot]
github-actions bot reviewed Aug 30, 2024
View reviewed changes
core/decoder.sv Outdated
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
instruction_o.rs1 = instr.rtype.rs1;
instruction_o.rs2 = instr.rtype.rs2;
instruction_o.rd = instr.rtype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.rtype.rd;
instruction_o.rd = instr.rtype.rd;

core/decoder.sv Outdated
@@ -1391,9 +1391,9 @@ module decoder
riscv::OpcodeJalr: begin
instruction_o.fu = CTRL_FLOW;
instruction_o.op = ariane_pkg::JALR;
instruction_o.rs1[4:0] = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rs1 = instr.itype.rs1;
instruction_o.rs1 = instr.itype.rs1;

core/decoder.sv Outdated
imm_select = IIMM;
instruction_o.rd[4:0] = instr.itype.rd;
instruction_o.rd = instr.itype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.itype.rd;
instruction_o.rd = instr.itype.rd;

core/decoder.sv Outdated
@@ -1402,21 +1402,21 @@ module decoder
riscv::OpcodeJal: begin
instruction_o.fu = CTRL_FLOW;
imm_select = JIMM;
instruction_o.rd[4:0] = instr.utype.rd;
instruction_o.rd = instr.utype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.utype.rd;
instruction_o.rd = instr.utype.rd;

core/decoder.sv Outdated
Comment on lines 1417 to 1418
imm_select = UIMM;
instruction_o.fu = ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
imm_select = UIMM;
instruction_o.fu = ALU;
imm_select = UIMM;
instruction_o.fu = ALU;

github-actions[bot]
github-actions bot reviewed Aug 30, 2024
View reviewed changes
core/decoder.sv Outdated
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
instruction_o.rs1 = instr.rtype.rs1;
instruction_o.rs2 = instr.rtype.rs2;
instruction_o.rd = instr.rtype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.rtype.rd;
instruction_o.rd = instr.rtype.rd;

core/decoder.sv Outdated
@@ -1402,21 +1402,21 @@
riscv::OpcodeJal: begin
instruction_o.fu = CTRL_FLOW;
imm_select = JIMM;
instruction_o.rd[4:0] = instr.utype.rd;
instruction_o.rd = instr.utype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.utype.rd;
instruction_o.rd = instr.utype.rd;

core/decoder.sv Outdated
Comment on lines 1417 to 1418
imm_select = UIMM;
instruction_o.fu = ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
imm_select = UIMM;
instruction_o.fu = ALU;
imm_select = UIMM;
instruction_o.fu = ALU;

github-actions[bot]
github-actions bot reviewed Aug 30, 2024
View reviewed changes
core/decoder.sv Outdated
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
instruction_o.rs1 = instr.rtype.rs1;
instruction_o.rs2 = instr.rtype.rs2;
instruction_o.rd = instr.rtype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.rtype.rd;
instruction_o.rd = instr.rtype.rd;

core/decoder.sv Outdated
Comment on lines 1417 to 1418
imm_select = UIMM;
instruction_o.fu = ALU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
imm_select = UIMM;
instruction_o.fu = ALU;
imm_select = UIMM;
instruction_o.fu = ALU;

github-actions[bot]
github-actions bot reviewed Aug 30, 2024
View reviewed changes
core/decoder.sv Outdated
instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU;
instruction_o.rs1 = instr.rtype.rs1;
instruction_o.rs2 = instr.rtype.rs2;
instruction_o.rd = instr.rtype.rd;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.rd = instr.rtype.rd;
instruction_o.rd = instr.rtype.rd;

core/decoder.sv Outdated
@@ -1102,9 +1102,9 @@
riscv::OpcodeMadd, riscv::OpcodeMsub, riscv::OpcodeNmsub, riscv::OpcodeNmadd: begin
if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static)
instruction_o.fu = FPU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.fu = FPU;
instruction_o.fu = FPU;

github-actions[bot]
github-actions bot reviewed Aug 30, 2024
View reviewed changes
core/decoder.sv Outdated
@@ -1102,9 +1102,9 @@ module decoder
riscv::OpcodeMadd, riscv::OpcodeMsub, riscv::OpcodeNmsub, riscv::OpcodeNmadd: begin
if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static)
instruction_o.fu = FPU;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
instruction_o.fu = FPU;
instruction_o.fu = FPU;

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✔️ successful run, report available here.

@JeanRochCoulon
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@ASintzoff ready to merge

@ASintzoff ASintzoff merged commit 8ef2859 into openhwgroup:master Aug 30, 2024
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@JeanRochCoulon JeanRochCoulon deleted the regaddrbits branch September 3, 2024 12:42
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@JeanRochCoulon @ASintzoff