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merge axi and l15 ports into noc port #1267

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merge axi and l15 ports into noc port #1267

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26 changes: 10 additions & 16 deletions core/cache_subsystem/wt_cache_subsystem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter int unsigned AxiAddrWidth = 0,
parameter int unsigned AxiDataWidth = 0,
parameter int unsigned AxiIdWidth = 0,
parameter type axi_req_t = ariane_axi::req_t,
parameter type axi_rsp_t = ariane_axi::resp_t
parameter type noc_req_t = ariane_axi::req_t,
parameter type noc_resp_t = ariane_axi::resp_t
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -57,15 +57,9 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
// writebuffer status
output logic wbuffer_empty_o,
output logic wbuffer_not_ni_o,
`ifdef PITON_ARIANE
// L15 (memory side)
output l15_req_t l15_req_o,
input l15_rtrn_t l15_rtrn_i
`else
// memory side
output axi_req_t axi_req_o,
input axi_rsp_t axi_resp_i
`endif
output noc_req_t noc_req_o,
input noc_resp_t noc_resp_i
// TODO: interrupt interface
);

Expand Down Expand Up @@ -153,16 +147,16 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
.dcache_data_i ( dcache_adapter ),
.dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ),
.dcache_rtrn_o ( adapter_dcache ),
.l15_req_o ( l15_req_o ),
.l15_rtrn_i ( l15_rtrn_i )
.l15_req_o ( noc_req_o ),
.l15_rtrn_i ( noc_rtrn_i )
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This is a typo - should be noc_resp_i instead of noc_rtrn_i. If you fix this, our simulation seems to be passing once again

);
`else
wt_axi_adapter #(
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidth ( AxiIdWidth ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
.axi_req_t ( noc_req_t ),
.axi_rsp_t ( noc_resp_t )
) i_adapter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand All @@ -176,8 +170,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
.dcache_data_i ( dcache_adapter ),
.dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ),
.dcache_rtrn_o ( adapter_dcache ),
.axi_req_o ( axi_req_o ),
.axi_resp_i ( axi_resp_i )
.axi_req_o ( noc_req_o ),
.axi_resp_i ( noc_resp_i )
);
`endif

Expand Down
35 changes: 14 additions & 21 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,8 @@ module cva6 import ariane_pkg::*; #(
parameter type axi_ar_chan_t = ariane_axi::ar_chan_t,
parameter type axi_aw_chan_t = ariane_axi::aw_chan_t,
parameter type axi_w_chan_t = ariane_axi::w_chan_t,
parameter type axi_req_t = ariane_axi::req_t,
parameter type axi_rsp_t = ariane_axi::resp_t
parameter type noc_req_t = ariane_axi::req_t,
parameter type noc_resp_t = ariane_axi::resp_t
) (
input logic clk_i,
input logic rst_ni,
Expand All @@ -39,14 +39,12 @@ module cva6 import ariane_pkg::*; #(
// RISC-V formal interface port (`rvfi`):
// Can be left open when formal tracing is not needed.
output ariane_pkg::rvfi_port_t rvfi_o,
// cvxif
output cvxif_pkg::cvxif_req_t cvxif_req_o,
input cvxif_pkg::cvxif_resp_t cvxif_resp_i,
// L15 (memory side)
output wt_cache_pkg::l15_req_t l15_req_o,
input wt_cache_pkg::l15_rtrn_t l15_rtrn_i,
// memory side, AXI Master
output axi_req_t axi_req_o,
input axi_rsp_t axi_resp_i
// memory side
output noc_req_t noc_req_o,
input noc_resp_t noc_resp_i
);

// ------------------------------------------
Expand Down Expand Up @@ -691,8 +689,8 @@ module cva6 import ariane_pkg::*; #(
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidth ( AxiIdWidth ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
.noc_req_t ( noc_req_t ),
.noc_resp_t ( noc_resp_t )
) i_cache_subsystem (
// to D$
.clk_i ( clk_i ),
Expand Down Expand Up @@ -720,14 +718,9 @@ module cva6 import ariane_pkg::*; #(
// write buffer status
.wbuffer_empty_o ( dcache_commit_wbuffer_empty ),
.wbuffer_not_ni_o ( dcache_commit_wbuffer_not_ni ),
`ifdef PITON_ARIANE
.l15_req_o ( l15_req_o ),
.l15_rtrn_i ( l15_rtrn_i )
`else
// memory side
.axi_req_o ( axi_req_o ),
.axi_resp_i ( axi_resp_i )
`endif
.noc_req_o ( noc_req_o ),
.noc_resp_i ( noc_resp_i )
);
end else begin

Expand All @@ -742,8 +735,8 @@ module cva6 import ariane_pkg::*; #(
.axi_ar_chan_t ( axi_ar_chan_t ),
.axi_aw_chan_t ( axi_aw_chan_t ),
.axi_w_chan_t ( axi_w_chan_t ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
.axi_req_t ( noc_req_t ),
.axi_rsp_t ( noc_resp_t )
) i_cache_subsystem (
// to D$
.clk_i ( clk_i ),
Expand Down Expand Up @@ -771,8 +764,8 @@ module cva6 import ariane_pkg::*; #(
.dcache_req_ports_i ( dcache_req_ports_ex_cache ),
.dcache_req_ports_o ( dcache_req_ports_cache_ex ),
// memory side
.axi_req_o ( axi_req_o ),
.axi_resp_i ( axi_resp_i )
.axi_req_o ( noc_req_o ),
.axi_resp_i ( noc_resp_i )
);
assign dcache_commit_wbuffer_not_ni = 1'b1;
end
Expand Down
8 changes: 5 additions & 3 deletions corev_apu/fpga/src/ariane_xilinx.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -697,7 +697,9 @@ ariane_axi::req_t axi_ariane_req;
ariane_axi::resp_t axi_ariane_resp;

ariane #(
.ArianeCfg ( ariane_soc::ArianeSocCfg )
.ArianeCfg ( ariane_soc::ArianeSocCfg ),
.noc_req_t ( ariane_axi::req_t ),
.noc_resp_t ( ariane_axi::resp_t )
) i_ariane (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
Expand All @@ -707,8 +709,8 @@ ariane #(
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
.debug_req_i ( debug_req_irq ),
.axi_req_o ( axi_ariane_req ),
.axi_resp_i ( axi_ariane_resp )
.noc_req_o ( axi_ariane_req ),
.noc_resp_i ( axi_ariane_resp )
);

`AXI_ASSIGN_FROM_REQ(slave[0], axi_ariane_req)
Expand Down
12 changes: 7 additions & 5 deletions corev_apu/openpiton/ariane_verilog_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -194,7 +194,9 @@ module ariane_verilog_wrap
};

ariane #(
.ArianeCfg ( ArianeOpenPitonCfg )
.ArianeCfg ( ArianeOpenPitonCfg ),
.noc_req_t ( wt_cache_pkg::l15_req_t ),
.noc_resp_t ( wt_cache_pkg::l15_rtrn_t )
) ariane (
.clk_i ( clk_i ),
.rst_ni ( spc_grst_l ),
Expand All @@ -205,11 +207,11 @@ module ariane_verilog_wrap
.time_irq_i ( time_irq ),
.debug_req_i ( debug_req ),
`ifdef PITON_ARIANE
.l15_req_o ( l15_req ),
.l15_rtrn_i ( l15_rtrn )
.noc_req_o ( l15_req ),
.noc_resp_i ( l15_rtrn )
`else
.axi_req_o ( axi_req ),
.axi_resp_i ( axi_resp )
.noc_req_o ( axi_req ),
.noc_resp_i ( axi_resp )
`endif
);

Expand Down
31 changes: 8 additions & 23 deletions corev_apu/src/ariane.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,8 @@ module ariane import ariane_pkg::*; #(
parameter type axi_ar_chan_t = ariane_axi::ar_chan_t,
parameter type axi_aw_chan_t = ariane_axi::aw_chan_t,
parameter type axi_w_chan_t = ariane_axi::w_chan_t,
parameter type axi_req_t = ariane_axi::req_t,
parameter type axi_rsp_t = ariane_axi::resp_t
parameter type noc_req_t = ariane_axi::req_t,
parameter type noc_resp_t = ariane_axi::resp_t
) (
input logic clk_i,
input logic rst_ni,
Expand All @@ -41,15 +41,9 @@ module ariane import ariane_pkg::*; #(
// Can be left open when formal tracing is not needed.
output rvfi_port_t rvfi_o,
`endif
`ifdef PITON_ARIANE
// L15 (memory side)
output wt_cache_pkg::l15_req_t l15_req_o,
input wt_cache_pkg::l15_rtrn_t l15_rtrn_i
`else
// memory side, AXI Master
output axi_req_t axi_req_o,
input axi_rsp_t axi_resp_i
`endif
output noc_req_t noc_req_o,
input noc_resp_t noc_resp_i
);

cvxif_pkg::cvxif_req_t cvxif_req;
Expand All @@ -63,8 +57,8 @@ module ariane import ariane_pkg::*; #(
.axi_ar_chan_t (axi_ar_chan_t),
.axi_aw_chan_t (axi_aw_chan_t),
.axi_w_chan_t (axi_w_chan_t),
.axi_req_t (axi_req_t),
.axi_rsp_t (axi_rsp_t)
.noc_req_t (noc_req_t),
.noc_resp_t (noc_resp_t)
) i_cva6 (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand All @@ -81,17 +75,8 @@ module ariane import ariane_pkg::*; #(
`endif
.cvxif_req_o ( cvxif_req ),
.cvxif_resp_i ( cvxif_resp ),
`ifdef PITON_ARIANE
.l15_req_o ( l15_req_o ),
.l15_rtrn_i ( l15_rtrn_i ),
.axi_req_o ( ),
.axi_resp_i ( '0 )
`else
.l15_req_o ( ),
.l15_rtrn_i ( '0 ),
.axi_req_o ( axi_req_o ),
.axi_resp_i ( axi_resp_i )
`endif
.noc_req_o ( noc_req_o ),
.noc_resp_i ( noc_resp_i )
);

if (ariane_pkg::CVXIF_PRESENT) begin : gen_example_coprocessor
Expand Down
8 changes: 5 additions & 3 deletions corev_apu/tb/ariane_testharness.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -607,7 +607,9 @@ module ariane_testharness #(
ariane_pkg::rvfi_port_t rvfi;

ariane #(
.ArianeCfg ( ariane_soc::ArianeSocCfg )
.ArianeCfg ( ariane_soc::ArianeSocCfg ),
.noc_req_t ( ariane_axi::req_t ),
.noc_resp_t ( ariane_axi::resp_t )
) i_ariane (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
Expand All @@ -625,8 +627,8 @@ module ariane_testharness #(
`else
.debug_req_i ( debug_req_core ),
`endif
.axi_req_o ( axi_ariane_req ),
.axi_resp_i ( axi_ariane_resp )
.noc_req_o ( axi_ariane_req ),
.noc_resp_i ( axi_ariane_resp )
);

`AXI_ASSIGN_FROM_REQ(slave[0], axi_ariane_req)
Expand Down