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[otbn,dv] Model a glitch on the STATUS register #24569

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[otbn,dv] Model a glitch on the STATUS register #24569

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16 changes: 15 additions & 1 deletion hw/ip/otbn/dv/otbnsim/sim/sim.py
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Original file line number Diff line number Diff line change
Expand Up @@ -215,7 +215,7 @@ def _step_idle(self, verbose: bool) -> StepRes:
# If we are IDLE and get an RMA request, we want to start a secure
# wipe, which will eventually put us into the LOCKED state.
if self.state.rma_req == LcTx.ON and not is_locked:
self.state.ext_regs.write('STATUS', Status.BUSY_SEC_WIPE_INT, True)
self.state.ext_regs.write('STATUS', Status.LOCKED, True)
self.state.set_fsm_state(FsmState.PRE_WIPE)
self.state.lock_after_wipe = True
self.state.wipe_rounds_done = 0
Expand Down Expand Up @@ -363,6 +363,20 @@ def _step_exec(self, verbose: bool) -> StepRes:
def _step_pre_wipe(self, verbose: bool) -> StepRes:
'''Step the simulation when waiting for a URND seed for wipe'''

# This is a bit of a hack to model a bug in the design where the STATUS
# register has a value of 0xff for a single cycle before it becomes
# BUSY_SEC_WIPE_INT.
#
# This happens when responding to an RMA request in _step_idle. If we
# update the register to be BUSY_SEC_WIPE_INT on each cycle (and the
# first one we are here in particular!), we will get analogous
# behaviour.
#
# TODO(#23903): Fix the bug in the design then drop this code (and
# change the STATUS value in _step_idle from LOCKED to
# BUSY_SEC_WIPE_INT).
self.state.ext_regs.write('STATUS', Status.BUSY_SEC_WIPE_INT, True)

# If we get an RMA request before we've managed to run any rounds of
# wiping then we are waiting for our first URND seed. The entropy
# complex might not be up, so we don't want to wait for a seed. Handle
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