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[test-triage] edn_sec_cm failures #24226

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jwnrt opened this issue Aug 6, 2024 · 1 comment · Fixed by #24237
Closed

[test-triage] edn_sec_cm failures #24226

jwnrt opened this issue Aug 6, 2024 · 1 comment · Fixed by #24237
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@vogelpi @h-filali
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Component:TestTriage Milestone:V2S Triage Priority Issue to be discussed with priority in the next triage meeting
Milestone
Earlgrey-PROD.M6

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@jwnrt
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jwnrt commented Aug 6, 2024

Hierarchy of regression failure

Block level

Failure Description

Started failing on 25th of July, 100% -> 0%.

  UVM_ERROR @  16565539 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  16565539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Steps to Reproduce

  • GitHub Revision: e4c5daa580
  • dvsim invocation command to reproduce the failure, inclusive of build and run seeds: 
    ./util/dvsim/dvsim.py hw/ip/edn/dv/edn_sim_cfg.hjson \
  -i edn_sec_cm \
  --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501 \
  --fixed-seed 34299359568848372465292589661168344678023408838600054326005816702909329066132 \
  --waves fsdb

Tests with similar or related failures

No response
@jwnrt jwnrt changed the title [test-triage] [test-triage] edn_sec_cm failures Aug 6, 2024
@hayleynewton hayleynewton added the Triage Priority Issue to be discussed with priority in the next triage meeting label Aug 6, 2024
@hayleynewton hayleynewton added this to the Earlgrey-PROD.M6 milestone Aug 6, 2024
vogelpi added a commit to vogelpi/opentitan that referenced this issue Aug 6, 2024
@vogelpi
[edn/dv] Allow flopped error output of prim_count to propagate to CSRs
3d535ba 
With lowRISC#24125, we added a register to the error output
of all prim_count instances. This adds an additional delay until errors
become actually visible via CSRs (e.g. main_sm_state, err_code). This
commit adds a corresponding wait statement to take this into
account.

This resolves lowRISC#24226.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
@vogelpi vogelpi mentioned this issue Aug 6, 2024
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@vogelpi
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vogelpi commented Aug 6, 2024 •
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Thanks for flagging this @jwnrt . This is related to the ECO fix (flopping prim_count error outputs). I've now filed a PR to fix this here: #24237.

vogelpi added a commit that referenced this issue Aug 8, 2024
@vogelpi
[edn/dv] Allow flopped error output of prim_count to propagate to CSRs
a43f5a3 
With #24125, we added a register to the error output
of all prim_count instances. This adds an additional delay until errors
become actually visible via CSRs (e.g. main_sm_state, err_code). This
commit adds a corresponding wait statement to take this into
account.

This resolves #24226.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
andreaskurth pushed a commit to andreaskurth/opentitan that referenced this issue Aug 10, 2024
@vogelpi @andreaskurth
[edn/dv] Allow flopped error output of prim_count to propagate to CSRs
b5389b1 
With lowRISC#24125, we added a register to the error output
of all prim_count instances. This adds an additional delay until errors
become actually visible via CSRs (e.g. main_sm_state, err_code). This
commit adds a corresponding wait statement to take this into
account.

This resolves lowRISC#24226.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
andreaskurth pushed a commit to andreaskurth/opentitan that referenced this issue Aug 12, 2024
@vogelpi @andreaskurth
[edn/dv] Allow flopped error output of prim_count to propagate to CSRs
cdb834b 
With lowRISC#24125, we added a register to the error output
of all prim_count instances. This adds an additional delay until errors
become actually visible via CSRs (e.g. main_sm_state, err_code). This
commit adds a corresponding wait statement to take this into
account.

This resolves lowRISC#24226.

This is a cherry pick of commit a43f5a3
to branch earlgrey_1.0.0.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
andreaskurth pushed a commit that referenced this issue Aug 12, 2024
@vogelpi @andreaskurth
[edn/dv] Allow flopped error output of prim_count to propagate to CSRs
68780db 
With #24125, we added a register to the error output
of all prim_count instances. This adds an additional delay until errors
become actually visible via CSRs (e.g. main_sm_state, err_code). This
commit adds a corresponding wait statement to take this into
account.

This resolves #24226.

This is a cherry pick of commit a43f5a3
to branch earlgrey_1.0.0.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
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[edn/dv] Allow flopped error output of prim_count to propagate to CSRs vogelpi/opentitan
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@hayleynewton @vogelpi @h-filali @jwnrt