GitHub - kholoud0/Verilog-ASIC-Designs-with-Testbenches: Collection of ASIC design projects and testbenches using Verilog. Includes various projects showcasing design and verification skills.

kholoud0 / Verilog-ASIC-Designs-with-Testbenches Public

Collection of ASIC design projects and testbenches using Verilog. Includes various projects showcasing design and verification skills.

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Name		Name	Last commit message	Last commit date
Latest commit History 38 Commits
16_Bit_Signed_ALU		16_Bit_Signed_ALU
8_16Bit_Register_File		8_16Bit_Register_File
ALU		ALU
Clock_Divider		Clock_Divider
UART_RX		UART_RX
UART_TX		UART_TX
Up_Dn_Counter		Up_Dn_Counter
serial 8-bit CRC		serial 8-bit CRC