[SYCL] Workaround for vec::load and vec::store #272
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This is a workaround for vec::load and vec::store to avoid unaligned load and stores. Signed-off-by: Vlad Romanov <vlad.romanov@intel.com>
vladimirlaz
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Jun 28, 2019
bb-sycl
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Apr 15, 2022
…n a loop
When untagging the stack, the compiler may emit a sequence like:
```
.LBB0_1:
st2g sp, [sp], #32
sub x8, x8, #32
cbnz x8, .LBB0_1
stg sp, [sp], #16
```
These stack adjustments cannot be described by CFI instructions.
This patch disables merging of SP update with untagging, i.e. makes the
compiler use an additional scratch register (there should be plenty
available at this point as we are in the epilogue) and generate:
```
mov x9, sp
mov x8, #256
stg x9, [x9], #16
.LBB0_1:
sub x8, x8, #32
st2g x9, [x9], #32
cbnz x8, .LBB0_1
add sp, sp, #272
```
Merging is disabled only when we need to generate asynchronous unwind
tables.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D114548
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This is a workaround for vec::load and vec::store to avoid unaligned
load and stores.
Signed-off-by: Vlad Romanov vlad.romanov@intel.com