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scheduler redesign #101

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romanovvlad
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Plan for next commits:

  1. Possibility to dump information about graph, like in current scheduler.
  2. Support for configuration of things like: lazy/eager, finish on destruction, fast scheduling, always blocking and so on.
  3. Documentation.
  4. More tests.
  5. True support for 1D sub - buffers.
  6. Convert comments to doxygen style.
  7. Implement "clean up" of commands.

The MemoryManager is supposed to be a single point of all allocations
in SYCL RT.

Signed-off-by: Vlad Romanov <vlad.romanov@intel.com>
Do not allocate memory on host in buffer_impl constructors when user's
ptr is provided. This is possible because the ownership of that memory
is given to the constructed SYCL buffer for the duration of it'
lifetime. The memory still need to be allocated in constructor that
takes iterators as they can point to non-consecutive memory(need
consecutive memory to interact with OpenCL).
This may improve performance as we avoid several memory allocation/copy.

As required by the Specification the host memory now always allocated
using allocator provided by user.

Moved methods that allocate, fill and copy memory to separate class.
Copy method was improved to support device to host and host to device
partial(aka CopyRect) version of copies. So, now the buffer_impl class
is decoupled from OpenCL.

Fix possible bug, now constructor from shared_ptr stores a copy of
shared_ptr in lambda to avoid deallocation of memory until buffer is
destructed or set_final_data is invoked to override destination for
updating host memory(aka copy back).

Signed-off-by: Vlad Romanov <vlad.romanov@intel.com>
Modified handler class so it creates special CG class.
CG class represents different types of command groups, such as kernel execution,
fill and so on. This is needed to decouple Scheduler from template parameters
introduced by lambda, various ranges and arguments.

Signed-off-by: Vlad Romanov <vlad.romanov@intel.com>
…ass.

The Requirement class is added as base non-templated class for accessor.
This class describes command group's requirement to memory object and
is used to build dependency graph in Scheduler.

Signed-off-by: Vlad Romanov <vlad.romanov@intel.com>
This patch introduces new scheduler which is enabled when SCHEDULER_20
macro is set(set by default). The new scheduler is based on accessor
rather on buffer, so it will support images.

Also now there are two commands that implements moving memory to
other contexts instead of one - alloca memory and memcpy. There is new
command - release memory which will be ran during the sycl::buffer or
sycl::image object destruction and releases memory instances for the
memory object.

Signed-off-by: Vlad Romanov <vlad.romanov@intel.com>
This patch fixes compilation of sycl application with default
compiler(without specifying -fsycl). To do this default KernelInfo
implementation is added + check that skips integration header
processing if specialization for KernelInfo(which is supposed to
come from integraion header) is not available.

Signed-off-by: Vlad Romanov <vlad.romanov@intel.com>
@romanovvlad romanovvlad force-pushed the private/vromanov/SchedulerRedesign branch from 824bfa7 to d75ca01 Compare April 23, 2019 09:44
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@vladimirlaz vladimirlaz left a comment

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Approve to start testing

@vladimirlaz vladimirlaz merged commit a945f31 into intel:sycl Apr 23, 2019
cl_int MapMemObject::enqueueImp() {
std::vector<cl_event> RawEvents =
Command::prepareEvents(detail::getSyclObjImpl(MQueue->get_context()));
assert(MDstReq.getNumOfDims() == 1);
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Debug build is broken by this line of code. Looks like it should be

Suggested change
assert(MDstReq.getNumOfDims() == 1);
assert(MDstReq.MDims == 1);

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Yes, you are right. Thanks.

vmaksimo pushed a commit to vmaksimo/llvm that referenced this pull request Feb 19, 2021
  CONFLICT (content): Merge conflict in clang/utils/TableGen/ClangProgModelBuiltinEmitter.cpp
steffenlarsen pushed a commit to steffenlarsen/llvm that referenced this pull request May 21, 2021
  CONFLICT (content): Merge conflict in llvm/include/llvm/LinkAllPasses.h
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3 participants