Add new implementations for completes and their display

- AVX512-vp2intersect bit and method
- AMX_TILE and AMX_INT8 method (bits were already implemented)
Add new test assertion for the new bits

src/display.rs

@@ -528,6 +528,25 @@ pub fn markdown<R: crate::CpuIdReader>(cpuid: crate::CpuId<R>) {
                     "AVX512F: AVX-512 foundation instructions",
                     info.has_avx512f(),
                 ),
+                RowGen::tuple("AVX512-4NNIW: 4NNIW instructions", info.has_avx512_4vnniw()),
+                RowGen::tuple(
+                    "AVX512-4FMAPS: 4FMAPS instructions",
+                    info.has_avx512_4fmaps(),
+                ),
+                RowGen::tuple(
+                    "AVX512-VP2INTERSECT: VP2INTERSECT instructions",
+                    info.has_avx512_vp2intersect(),
+                ),
+                RowGen::tuple("AMX_BF16: AMX_BF16 instructions", info.has_amx_bf16()),
+                RowGen::tuple(
+                    "AVX512_FP16: AVX512_FP16 instructions",
+                    info.has_avx512_fp16(),
+                ),
+                RowGen::tuple("AMX_TILE: Tile Architecture support", info.has_amx_tile()),
+                RowGen::tuple(
+                    "AMX_INT8: Tile Computational Operation on 8-bit integers",
+                    info.has_amx_tile(),
+                ),
                 RowGen::tuple(
                     "AVX512DQ: double & quadword instructions",
                     info.has_avx512dq(),

src/lib.rs

@@ -3690,6 +3690,15 @@ impl ExtendedFeatures {
         self.edx.contains(ExtendedFeaturesEdx::AVX512_4FMAPS)
     }
 
+    /// Supports AVX512_VP2INTERSECT.
+    ///
+    /// # Platforms
+    /// ❌ AMD (reserved) ✅ Intel
+    #[inline]
+    pub const fn has_avx512_vp2intersect(&self) -> bool {
+        self.edx.contains(ExtendedFeaturesEdx::AVX512_VP2INTERSECT)
+    }
+
     /// Supports AMX_BF16.
     ///
     /// # Platforms
@@ -3699,14 +3708,32 @@ impl ExtendedFeatures {
         self.edx.contains(ExtendedFeaturesEdx::AMX_BF16)
     }
 
-    /// Supports AVX_FP16.
+    /// Supports AVX512_FP16.
     ///
     /// # Platforms
     /// ❌ AMD (reserved) ✅ Intel
     #[inline]
     pub const fn has_avx512_fp16(&self) -> bool {
         self.edx.contains(ExtendedFeaturesEdx::AVX512_FP16)
     }
+
+    /// Supports AMX_TILE.
+    ///
+    /// # Platforms
+    /// ❌ AMD (reserved) ✅ Intel
+    #[inline]
+    pub const fn has_amx_tile(&self) -> bool {
+        self.edx.contains(ExtendedFeaturesEdx::AMX_TILE)
+    }
+
+    /// Supports AMX_INT8.
+    ///
+    /// # Platforms
+    /// ❌ AMD (reserved) ✅ Intel
+    #[inline]
+    pub const fn has_amx_int8(&self) -> bool {
+        self.edx.contains(ExtendedFeaturesEdx::AMX_INT8)
+    }
 }
 
 impl Debug for ExtendedFeatures {
@@ -3852,6 +3879,8 @@ bitflags! {
         const AVX512_4VNNIW = 1 << 2;
         /// Bit 03: AVX512_4FMAPS. (Intel® Xeon Phi™ only).
         const AVX512_4FMAPS = 1 << 3;
+        /// Bit 08: AVX512_VP2INTERSECT.
+        const AVX512_VP2INTERSECT = 1 << 8;
         /// Bit 22: AMX-BF16. If 1, the processor supports tile computational operations on bfloat16 numbers.
         const AMX_BF16 = 1 << 22;
         /// Bit 23: AVX512_FP16.

src/tests/i5_3337u.rs

@@ -291,6 +291,14 @@ fn extended_features() {
     assert!(tpfeatures2.has_smap());
     assert!(tpfeatures2.has_clflushopt());
     assert!(tpfeatures2.has_processor_trace());
+
+    assert!(!tpfeatures2.has_avx512_4vnniw());
+    assert!(!tpfeatures2.has_avx512_4fmaps());
+    assert!(!tpfeatures2.has_avx512_vp2intersect());
+    assert!(!tpfeatures2.has_amx_bf16());
+    assert!(!tpfeatures2.has_avx512_fp16());
+    assert!(!tpfeatures2.has_amx_tile());
+    assert!(!tpfeatures2.has_amx_int8());
 }
 
 #[test]