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SAR via explicit bit twiddling
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gcolvin authored and axic committed Oct 3, 2017
1 parent 2021c21 commit 6ff0052
Showing 1 changed file with 12 additions and 4 deletions.
16 changes: 12 additions & 4 deletions libevm/VM.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -654,16 +654,24 @@ void VM::interpretCases()
{
ON_OP();
updateIOGas();

static u256 const hibit = u256(1) << 255;
static u256 const allbits =
u256("0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff");

s256 shiftee = m_SP[1];
u256 shiftee = m_SP[1];
if (m_SP[0] >= 256)
{
if (shiftee < 0)
m_SPP[0] = u256(-1);
if (shiftee & hibit)
m_SPP[0] = allbits;
else
m_SPP[0] = 0;
}
else
{
m_SPP[0] = u256(shiftee >> uint64_t(m_SP[0]));
uint64_t amount = uint64_t(m_SP[0]);
m_SPP[0] = shiftee >> amount;
m_SPP[0] |= allbits << (256 - amount);
}
}
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