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ESP32-C6 cleanup #148

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Mar 13, 2023
Merged

ESP32-C6 cleanup #148

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79 changes: 62 additions & 17 deletions esp-wifi/src/common_adapter/common_adapter_esp32c6.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -211,29 +211,74 @@ pub(crate) unsafe extern "C" fn read_mac(

pub(crate) fn init_clocks() {
unsafe {
// PERIP_CLK_EN0
((0x600c0000 + 0x10) as *mut u32).write_volatile(0xffffffff);
// PERIP_CLK_EN1
((0x600c0000 + 0x14) as *mut u32).write_volatile(0xffffffff);
}
let pmu = &*esp32c6::PMU::PTR;

pmu.hp_sleep_icg_modem
.modify(|_, w| w.hp_sleep_dig_icg_modem_code().variant(0));
pmu.hp_modem_icg_modem
.modify(|_, w| w.hp_modem_dig_icg_modem_code().variant(1));
pmu.hp_active_icg_modem
.modify(|_, w| w.hp_active_dig_icg_modem_code().variant(2));
pmu.imm_modem_icg
.as_ptr()
.write_volatile(pmu.imm_modem_icg.as_ptr().read_volatile() | 1 << 31);
pmu.imm_sleep_sysclk
.as_ptr()
.write_volatile(pmu.imm_sleep_sysclk.as_ptr().read_volatile() | 1 << 28);

let syscon_clk_conf_power_st = (0x600A9800 + 12) as *mut u32;
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 28);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 4 << 24);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 20);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 16);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 12);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 8);

let lp_clk_conf_power_st = (MODEM_LPCON + 8 * 4) as *mut u32;
lp_clk_conf_power_st.write_volatile(lp_clk_conf_power_st.read_volatile() | 6 << 28);
lp_clk_conf_power_st.write_volatile(lp_clk_conf_power_st.read_volatile() | 6 << 24);
lp_clk_conf_power_st.write_volatile(lp_clk_conf_power_st.read_volatile() | 6 << 20);
lp_clk_conf_power_st.write_volatile(lp_clk_conf_power_st.read_volatile() | 6 << 16);

const MODEM_LPCON: u32 = 0x600AF000;
let wifi_lp_clk_con = (MODEM_LPCON + 4 * 3) as *mut u32;
const CLK_WIFIPWR_LP_SEL_OSC_SLOW: u32 = 0;
const CLK_WIFIPWR_LP_SEL_OSC_FAST: u32 = 1;
const CLK_WIFIPWR_LP_SEL_XTAL32K: u32 = 3;
const CLK_WIFIPWR_LP_SEL_XTAL: u32 = 2;
const CLK_WIFIPWR_LP_DIV_NUM_SHIFT: u32 = 4;
const CLK_WIFIPWR_LP_DIV_NUM_MASK: u32 = 0b1111_1111_1111;
const CLK_WIFIPWR_EN: u32 = 0;

// modem_clock_hal_deselect_all_wifi_lpclk_source
wifi_lp_clk_con.write_volatile(
wifi_lp_clk_con.read_volatile()
& !(1 << CLK_WIFIPWR_LP_SEL_OSC_SLOW
| 1 << CLK_WIFIPWR_LP_SEL_OSC_FAST
| 1 << CLK_WIFIPWR_LP_SEL_XTAL32K
| 1 << CLK_WIFIPWR_LP_SEL_XTAL),
);

// APB_CTRL_WIFI_CLK_EN_REG
unsafe {
((0x60026000 + 0x14) as *mut u32).write_volatile(0xffffffff);
// modem_clock_hal_select_wifi_lpclk_source
wifi_lp_clk_con
.write_volatile(wifi_lp_clk_con.read_volatile() | 1 << CLK_WIFIPWR_LP_SEL_OSC_SLOW);

// modem_lpcon_ll_set_wifi_lpclk_divisor_value
wifi_lp_clk_con.write_volatile(
wifi_lp_clk_con.read_volatile()
& !(CLK_WIFIPWR_LP_DIV_NUM_MASK << CLK_WIFIPWR_LP_DIV_NUM_SHIFT)
| 0 << CLK_WIFIPWR_LP_DIV_NUM_SHIFT,
);

// modem_lpcon_ll_enable_wifipwr_clock
let clk_conf = (MODEM_LPCON + 6 * 3) as *mut u32;
clk_conf.write_volatile(clk_conf.read_volatile() | 1 << CLK_WIFIPWR_EN);
}
}

#[allow(unused)]
pub(crate) fn wifi_reset_mac() {
const SYSCON_WIFI_RST_EN_REG: *mut u32 = (0x60026000 + 0x18) as *mut u32;
const SYSTEM_MAC_RST: u32 = 1 << 2;

unsafe {
SYSCON_WIFI_RST_EN_REG
.write_volatile(SYSCON_WIFI_RST_EN_REG.read_volatile() | SYSTEM_MAC_RST);
SYSCON_WIFI_RST_EN_REG
.write_volatile(SYSCON_WIFI_RST_EN_REG.read_volatile() & !SYSTEM_MAC_RST);
}
// empty
}

#[no_mangle]
Expand Down
6 changes: 0 additions & 6 deletions esp-wifi/src/lib.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -123,9 +123,6 @@ pub fn initialize(
return Err(InitializationError::WrongClockConfig);
}

#[cfg(feature = "esp32c6")]
wifi::os_adapter_chip_specific::setup();

phy_mem_init();
init_rng(rng);
init_tasks();
Expand Down Expand Up @@ -158,9 +155,6 @@ pub fn initialize(
crate::ble::ble_init();
}

#[cfg(feature = "esp32c6")]
wifi::os_adapter_chip_specific::run_after_initialze_hack();

Ok(())
}

Expand Down
15 changes: 6 additions & 9 deletions esp-wifi/src/timer_esp32c6.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -44,9 +44,12 @@ pub fn setup_timer_isr(systimer: Alarm<Target, 0>) {
esp32c6_hal::interrupt::enable(Interrupt::WIFI_PWR, hal::interrupt::Priority::Priority1)
.unwrap();

#[cfg(feature = "wifi")]
esp32c6_hal::interrupt::enable(Interrupt::WIFI_BB, hal::interrupt::Priority::Priority1)
.unwrap();
// make sure to disable WIFI_BB by mapping it to CPU interrupt 31 which is masked by default
// for some reason for this interrupt, mapping it to 0 doesn't deactivate it
let interrupt_core0 = unsafe { &*esp32c6::INTERRUPT_CORE0::PTR };
interrupt_core0
.wifi_bb_intr_map
.write(|w| w.wifi_bb_intr_map().variant(31));

#[cfg(feature = "ble")]
{
Expand Down Expand Up @@ -105,12 +108,6 @@ fn WIFI_PWR() {
};
}

#[cfg(feature = "wifi")]
#[interrupt]
fn WIFI_BB() {
// just do nothing at all - we only want to make sure to not run into the default handler
}

#[cfg(feature = "ble")]
#[interrupt]
fn RWBT() {
Expand Down
78 changes: 0 additions & 78 deletions esp-wifi/src/wifi/os_adapter_esp32c6.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -155,84 +155,6 @@ pub(crate) unsafe extern "C" fn wifi_clock_disable() {
}
}

pub(crate) fn setup() {
unsafe {
let pmu = &*esp32c6::PMU::PTR;

pmu.hp_sleep_icg_modem
.modify(|_, w| w.hp_sleep_dig_icg_modem_code().variant(0));
pmu.hp_modem_icg_modem
.modify(|_, w| w.hp_modem_dig_icg_modem_code().variant(1));
pmu.hp_active_icg_modem
.modify(|_, w| w.hp_active_dig_icg_modem_code().variant(2));
pmu.imm_modem_icg
.as_ptr()
.write_volatile(pmu.imm_modem_icg.as_ptr().read_volatile() | 1 << 31);
pmu.imm_sleep_sysclk
.as_ptr()
.write_volatile(pmu.imm_sleep_sysclk.as_ptr().read_volatile() | 1 << 28);

let syscon_clk_conf_power_st = (0x600A9800 + 12) as *mut u32;
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 28);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 4 << 24);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 20);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 16);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 12);
syscon_clk_conf_power_st.write_volatile(syscon_clk_conf_power_st.read_volatile() | 6 << 8);

let lp_clk_conf_power_st = (MODEM_LPCON + 8 * 4) as *mut u32;
lp_clk_conf_power_st.write_volatile(lp_clk_conf_power_st.read_volatile() | 6 << 28);
lp_clk_conf_power_st.write_volatile(lp_clk_conf_power_st.read_volatile() | 6 << 24);
lp_clk_conf_power_st.write_volatile(lp_clk_conf_power_st.read_volatile() | 6 << 20);
lp_clk_conf_power_st.write_volatile(lp_clk_conf_power_st.read_volatile() | 6 << 16);

const MODEM_LPCON: u32 = 0x600AF000;
let wifi_lp_clk_con = (MODEM_LPCON + 4 * 3) as *mut u32;
const CLK_WIFIPWR_LP_SEL_OSC_SLOW: u32 = 0;
const CLK_WIFIPWR_LP_SEL_OSC_FAST: u32 = 1;
const CLK_WIFIPWR_LP_SEL_XTAL32K: u32 = 3;
const CLK_WIFIPWR_LP_SEL_XTAL: u32 = 2;
const CLK_WIFIPWR_LP_DIV_NUM_SHIFT: u32 = 4;
const CLK_WIFIPWR_LP_DIV_NUM_MASK: u32 = 0b1111_1111_1111;
const CLK_WIFIPWR_EN: u32 = 0;

// modem_clock_hal_deselect_all_wifi_lpclk_source
wifi_lp_clk_con.write_volatile(
wifi_lp_clk_con.read_volatile()
& !(1 << CLK_WIFIPWR_LP_SEL_OSC_SLOW
| 1 << CLK_WIFIPWR_LP_SEL_OSC_FAST
| 1 << CLK_WIFIPWR_LP_SEL_XTAL32K
| 1 << CLK_WIFIPWR_LP_SEL_XTAL),
);

// modem_clock_hal_select_wifi_lpclk_source
wifi_lp_clk_con
.write_volatile(wifi_lp_clk_con.read_volatile() | 1 << CLK_WIFIPWR_LP_SEL_OSC_SLOW);

// modem_lpcon_ll_set_wifi_lpclk_divisor_value
wifi_lp_clk_con.write_volatile(
wifi_lp_clk_con.read_volatile()
& !(CLK_WIFIPWR_LP_DIV_NUM_MASK << CLK_WIFIPWR_LP_DIV_NUM_SHIFT)
| 0 << CLK_WIFIPWR_LP_DIV_NUM_SHIFT,
);

// modem_lpcon_ll_enable_wifipwr_clock
let clk_conf = (MODEM_LPCON + 6 * 3) as *mut u32;
clk_conf.write_volatile(clk_conf.read_volatile() | 1 << CLK_WIFIPWR_EN);
}
}

/// This is needed since apparently `esp_wifi_init` enables the WIFI_BB interrupt
/// but it doesn't register a callback to handle it.
///
/// This is to disable the WIFI_BB interrupt after initialization.
pub(crate) fn run_after_initialze_hack() {
unsafe {
// try to disable the WIFI_BB interrupt
(0x6001000c as *mut u32).write_volatile(0);
}
}

pub(crate) unsafe extern "C" fn regdma_link_set_write_wait_content_dummy(
_arg1: *mut esp_wifi_sys::c_types::c_void,
_arg2: u32,
Expand Down