dalance · dalance · Aug 1, 2022 · Jul 20, 2022 · Jul 20, 2022 · Jul 20, 2022
diff --git a/sv-parser-parser/src/keywords.rs b/sv-parser-parser/src/keywords.rs
@@ -1446,8 +1446,6 @@ pub(crate) const KEYWORDS_1800_2017: &[&str] = &[
 ];
 
 pub(crate) const KEYWORDS_DIRECTIVE: &[&str] = &[
-    "__FILE__",
-    "__LINE__",
     "begin_keywords",
     "celldefine",
     "default_nettype",

diff --git a/sv-parser-pp/src/preprocess.rs b/sv-parser-pp/src/preprocess.rs
diff --git a/sv-parser-pp/testcases/IEEE18002017_keywords_if2_13642005.sv b/sv-parser-pp/testcases/IEEE18002017_keywords_if2_13642005.sv
@@ -0,0 +1,8 @@
+
+`begin_keywords "1364-2005" // use IEEE Std 1364-2005 Verilog keywords
+interface if2 (); // ERROR: "interface" is not a keyword in 1364-2005
+  // This interface should pass the preprocessor, but not the main parser
+  // because the identifiers `interface` and `endinterface` are not reserved
+  // keywords in IEEE1364-2005.
+endinterface // ERROR: "endinterface" is not a keyword in 1364-2005
+`end_keywords
diff --git a/sv-parser-pp/testcases/IEEE18002017_keywords_m2_13642001.sv b/sv-parser-pp/testcases/IEEE18002017_keywords_m2_13642001.sv
@@ -0,0 +1,8 @@
+
+`begin_keywords "1364-2001"
+module m2 ();
+  // "logic" is NOT a reserved keyword in IEEE1364-2001.
+  // This module should pass both the preprocessor, AND the main parser.
+  reg [63:0] logic;
+endmodule
+`end_keywords
diff --git a/sv-parser-pp/testcases/IEEE18002017_keywords_m2_18002005.sv b/sv-parser-pp/testcases/IEEE18002017_keywords_m2_18002005.sv
@@ -0,0 +1,8 @@
+
+`begin_keywords "1800-2005"
+module m2 ();
+  // "logic" IS a reserved keyword in IEEE1800-2005.
+  // This module should pass both the preprocessor, but NOT the main parser.
+  reg [63:0] logic;
+endmodule
+`end_keywords
diff --git a/sv-parser-pp/testcases/IEEE18002017_macro_argument_expansion.sv b/sv-parser-pp/testcases/IEEE18002017_macro_argument_expansion.sv
@@ -0,0 +1,10 @@
+/* IEEE1800-2017 Clause 22.5.1 page 679
+*/
+
+`define max(a,b)((a) > (b) ? (a) : (b))
+`define TOP(a,b) a + b
+
+module m;
+assign n = `max(p+q, r+s) ;
+assign z = `TOP( `TOP(b,1), `TOP(42,a) );
+endmodule
diff --git a/sv-parser-pp/testcases/IEEE18002017_macro_delimit_tokens.sv b/sv-parser-pp/testcases/IEEE18002017_macro_delimit_tokens.sv
@@ -0,0 +1,7 @@
+/* IEEE1800-2017 Clause 22.5.1 page 680
+*/
+
+`define append(f) f``_master
+
+module `append(clock);
+endmodule
diff --git a/sv-parser-pp/testcases/test6.sv → ...estcases/IEEE18002017_macro_mix_quotes.sv b/sv-parser-pp/testcases/test6.sv → ...estcases/IEEE18002017_macro_mix_quotes.sv
@@ -1,3 +1,6 @@
+/* IEEE1800-2017 Clause 22.5.1 page 680
+*/
+
 `define msg(x,y) `"x: `\`"y`\`"`"
 
 module a;

diff --git a/sv-parser-pp/testcases/IEEE18002017_macro_noexpand_string.sv b/sv-parser-pp/testcases/IEEE18002017_macro_noexpand_string.sv
@@ -0,0 +1,13 @@
+/* IEEE1800-2017 Clause 22.5.1 page 679
+*/
+
+module main;
+`define HI Hello
+`define LO "`HI, world"
+`define H(x) "Hello, x"
+initial begin
+  $display("`HI, world");
+  $display(`LO);
+  $display(`H(world));
+end
+endmodule
diff --git a/sv-parser-pp/testcases/IEEE18002017_macro_with_defaults.sv b/sv-parser-pp/testcases/IEEE18002017_macro_with_defaults.sv
@@ -0,0 +1,25 @@
+/* IEEE1800-2017 Clause 22.5.1 page 678
+* NOTE: Illegal cases are not included in this testcase.
+* NOTE: Use of EMPTY is suggested on page 679
+*/
+
+`define MACRO1(a=5,b="B",c) $display(a,,b,,c);
+`define MACRO2(a=5, b, c="C") $display(a,,b,,c);
+`define MACRO3(a=5, b=0, c="C") $display(a,,b,,c);
+
+`define EMPTY
+
+module m;
+initial begin
+  `MACRO1 ( , 2, 3 )
+  `MACRO1 ( 1 , , 3 )
+  `MACRO1 ( , 2, )
+  `MACRO2 (1, , 3)
+  `MACRO2 (, 2, )
+  `MACRO2 (, 2)
+  `MACRO3 ( 1 )
+  `MACRO3 ( )
+
+  `MACRO3 (`EMPTY,`EMPTY,`EMPTY)
+end
+endmodule
diff --git a/sv-parser-pp/testcases/IEEE18002017_macro_without_defaults.sv b/sv-parser-pp/testcases/IEEE18002017_macro_without_defaults.sv
@@ -0,0 +1,13 @@
+/* IEEE1800-2017 Clause 22.5.1 page 677
+* NOTE: Illegal cases are not included in this testcase.
+*/
+
+`define D(x,y) initial $display("start", x , y, "end");
+
+module m;
+  `D( "msg1" , "msg2" )
+  `D( " msg1", )
+  `D(, "msg2 ")
+  `D(,)
+  `D( , )
+endmodule
diff --git a/sv-parser-pp/testcases/celldefine.sv b/sv-parser-pp/testcases/celldefine.sv
@@ -0,0 +1,13 @@
+// IEEE1800-2017 Clause 22.10
+// The directives `celldefine and `endcelldefine tag modules as cell modules.
+// Cells are used by certain PLI routines and may be useful for applications
+// such as delay calculations. It is advisable to pair each `celldefine with an
+// `endcelldefine, but it is not required. The latest occurrence of either
+// directive in the source controls whether modules are tagged as cell modules.
+// More than one of these pairs may appear in a single source description.
+// These directives may appear anywhere in the source description, but it is
+// recommended that the directives be specified outside any design elements.
+//  The `resetall directive includes the effects of a `endcelldefine directive.
+`celldefine
+`endcelldefine
+// This file should be emitted from the preprocessor unchanged.
diff --git a/sv-parser-pp/testcases/default_nettype.sv b/sv-parser-pp/testcases/default_nettype.sv
@@ -0,0 +1,22 @@
+// IEEE1800-2017 Clause 22.8
+// The directive `default_nettype controls the net type created for implicit
+// net declarations. It can be used only outside design elements. Multiple
+// `default_nettype directives are allowed. The latest occurrence of this
+// directive in the source controls the type of nets that will be implicitly
+// declared.
+// When no `default_nettype directive is present or if the `resetall directive
+// is specified, implicit nets are of type wire. When the `default_nettype is
+// set to none, all nets shall be explicitly declared. If a net is not
+// explicitly declared, an error is generated.
+`default_nettype wire // Comment immmediately after keyword+space
+`default_nettype tri
+`default_nettype tri0
+`default_nettype tri1
+`default_nettype wand
+`default_nettype triand
+`default_nettype wor
+`default_nettype trior
+`default_nettype trireg
+`default_nettype uwire
+`default_nettype none// Comment immmediately after keyword
+// This file should be emitted from the preprocessor unchanged.
diff --git a/sv-parser-pp/testcases/test12.sv → sv-parser-pp/testcases/escaped_identifier.sv b/sv-parser-pp/testcases/test12.sv → sv-parser-pp/testcases/escaped_identifier.sv
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_keywords_if2_13642005.sv b/sv-parser-pp/testcases/expected/IEEE18002017_keywords_if2_13642005.sv
@@ -0,0 +1,8 @@
+
+`begin_keywords "1364-2005" // use IEEE Std 1364-2005 Verilog keywords
+interface if2 (); // ERROR: "interface" is not a keyword in 1364-2005
+  // This interface should pass the preprocessor, but not the main parser
+  // because the identifiers `interface` and `endinterface` are not reserved
+  // keywords in IEEE1364-2005.
+endinterface // ERROR: "endinterface" is not a keyword in 1364-2005
+`end_keywords
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_keywords_m2_13642001.sv b/sv-parser-pp/testcases/expected/IEEE18002017_keywords_m2_13642001.sv
@@ -0,0 +1,8 @@
+
+`begin_keywords "1364-2001"
+module m2 ();
+  // "logic" is NOT a reserved keyword in IEEE1364-2001.
+  // This module should pass both the preprocessor, AND the main parser.
+  reg [63:0] logic;
+endmodule
+`end_keywords
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_keywords_m2_18002005.sv b/sv-parser-pp/testcases/expected/IEEE18002017_keywords_m2_18002005.sv
@@ -0,0 +1,8 @@
+
+`begin_keywords "1800-2005"
+module m2 ();
+  // "logic" IS a reserved keyword in IEEE1800-2005.
+  // This module should pass both the preprocessor, but NOT the main parser.
+  reg [63:0] logic;
+endmodule
+`end_keywords
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_macro_argument_expansion.sv b/sv-parser-pp/testcases/expected/IEEE18002017_macro_argument_expansion.sv
@@ -0,0 +1,10 @@
+/* IEEE1800-2017 Clause 22.5.1 page 679
+*/
+
+`define max(a,b)((a) > (b) ? (a) : (b))
+`define TOP(a,b) a + b
+
+module m;
+assign n = ((p+q) > (r+s) ? (p+q) : (r+s)) ;
+assign z = b + 1 + 42 + a;
+endmodule
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_macro_delimit_tokens.sv b/sv-parser-pp/testcases/expected/IEEE18002017_macro_delimit_tokens.sv
@@ -0,0 +1,7 @@
+/* IEEE1800-2017 Clause 22.5.1 page 680
+*/
+
+`define append(f) f``_master
+
+module clock_master;
+endmodule
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_macro_mix_quotes.sv b/sv-parser-pp/testcases/expected/IEEE18002017_macro_mix_quotes.sv
@@ -0,0 +1,10 @@
+/* IEEE1800-2017 Clause 22.5.1 page 680
+*/
+
+`define msg(x,y) `"x: `\`"y`\`"`"
+
+module a;
+initial begin
+$display("left side: \"right side\"");
+end
+endmodule
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_macro_noexpand_string.sv b/sv-parser-pp/testcases/expected/IEEE18002017_macro_noexpand_string.sv
@@ -0,0 +1,13 @@
+/* IEEE1800-2017 Clause 22.5.1 page 679
+*/
+
+module main;
+`define HI Hello
+`define LO "`HI, world"
+`define H(x) "Hello, x"
+initial begin
+  $display("`HI, world");
+  $display("`HI, world");
+  $display("Hello, x");
+end
+endmodule
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_macro_with_defaults.sv b/sv-parser-pp/testcases/expected/IEEE18002017_macro_with_defaults.sv
@@ -0,0 +1,25 @@
+/* IEEE1800-2017 Clause 22.5.1 page 678
+* NOTE: Illegal cases are not included in this testcase.
+* NOTE: Use of EMPTY is suggested on page 679
+*/
+
+`define MACRO1(a=5,b="B",c) $display(a,,b,,c);
+`define MACRO2(a=5, b, c="C") $display(a,,b,,c);
+`define MACRO3(a=5, b=0, c="C") $display(a,,b,,c);
+
+`define EMPTY
+
+module m;
+initial begin
+  $display(5,,2,,3);
+  $display(1,,"B",,3);
+  $display(5,,2,,);
+  $display(1,,,,3);
+  $display(5,,2,,"C");
+  $display(5,,2,,"C");
+  $display(1,,0,,"C");
+  $display(5,,0,,"C");
+
+  $display(,,,,);
+end
+endmodule
diff --git a/sv-parser-pp/testcases/expected/IEEE18002017_macro_without_defaults.sv b/sv-parser-pp/testcases/expected/IEEE18002017_macro_without_defaults.sv
@@ -0,0 +1,13 @@
+/* IEEE1800-2017 Clause 22.5.1 page 677
+* NOTE: Illegal cases are not included in this testcase.
+*/
+
+`define D(x,y) initial $display("start", x , y, "end");
+
+module m;
+  initial $display("start", "msg1"  , "msg2", "end");
+  initial $display("start", " msg1"  , , "end");
+  initial $display("start",  , "msg2 ", "end");
+  initial $display("start",  , , "end");
+  initial $display("start",  , , "end");
+endmodule
diff --git a/sv-parser-pp/testcases/expected/escaped_identifier.sv b/sv-parser-pp/testcases/expected/escaped_identifier.sv
@@ -0,0 +1,3 @@
+module a;
+reg \`~!-_=+\|[]{};:'"",./<>?  ;
+endmodule
diff --git a/sv-parser-pp/testcases/expected/ifdef_nested.sv b/sv-parser-pp/testcases/expected/ifdef_nested.sv
@@ -0,0 +1,5 @@
+module A;
+wire a = 1'b0;
+
+
+endmodule
diff --git a/sv-parser-pp/testcases/expected/ifdef_predefined.sv b/sv-parser-pp/testcases/expected/ifdef_predefined.sv
@@ -0,0 +1,7 @@
+module and_op (a, b, c);
+output a;
+input b, c;
+
+wire a = b & c;
+
+endmodule
diff --git a/sv-parser-pp/testcases/expected/ifdef_undefined.sv b/sv-parser-pp/testcases/expected/ifdef_undefined.sv
@@ -0,0 +1,7 @@
+module and_op (a, b, c);
+output a;
+input b, c;
+
+and a1 (a,b,c);
+
+endmodule
diff --git a/sv-parser-pp/testcases/expected/ifndef_undefined.sv b/sv-parser-pp/testcases/expected/ifndef_undefined.sv
@@ -0,0 +1,5 @@
+// pragma translate_off
+module A;
+endmodule
+// pragma translate_on
+
diff --git a/sv-parser-pp/testcases/test2.sv → ...r-pp/testcases/expected/include_ignore.sv b/sv-parser-pp/testcases/test2.sv → ...r-pp/testcases/expected/include_ignore.sv
@@ -1,3 +1,3 @@
 module and_op (a, b, c);
-`include "test2.svh"
+ 
 endmodule
diff --git a/sv-parser-pp/testcases/expected/include_noindent.sv b/sv-parser-pp/testcases/expected/include_noindent.sv
@@ -0,0 +1,8 @@
+module and_op (a, b, c);
+output a;
+input b, c;
+
+and a1 (a,b,c);
+
+
+endmodule
diff --git a/sv-parser-pp/testcases/expected/include_quoted_c.sv b/sv-parser-pp/testcases/expected/include_quoted_c.sv
@@ -0,0 +1,9 @@
+// Based on last example of IEEE1800-2017 Clause 22.5.1, page 680.
+`define APPEND_SVH(path) `"path.svh`"
+module and_op (a, b, c);
+output a;
+input b, c;
+
+and a1 (a,b,c);
+
+endmodule
diff --git a/sv-parser-pp/testcases/expected/include_quoted_d.sv b/sv-parser-pp/testcases/expected/include_quoted_d.sv
@@ -0,0 +1,8 @@
+`define PATH "included.svh"
+module and_op (a, b, c);
+output a;
+input b, c;
+
+and a1 (a,b,c);
+
+endmodule
diff --git a/sv-parser-pp/testcases/expected/include_sameline_comment.sv b/sv-parser-pp/testcases/expected/include_sameline_comment.sv
@@ -0,0 +1,8 @@
+module and_op (a, b, c);
+output a;
+input b, c;
+
+and a1 (a,b,c);
+
+ // comment
+endmodule
diff --git a/sv-parser-pp/testcases/expected/include_withindent.sv b/sv-parser-pp/testcases/expected/include_withindent.sv
@@ -0,0 +1,9 @@
+module and_op (a, b, c);
+  // a
+  output a;
+input b, c;
+
+and a1 (a,b,c);
+
+
+endmodule
diff --git a/sv-parser-pp/testcases/expected/macro_FILE.sv b/sv-parser-pp/testcases/expected/macro_FILE.sv
@@ -0,0 +1,15 @@
+// __FILE__ = `__FILE__
+
+// This block SHOULD be emitted from the preprocessor.
+
+
+// Emitted instead.
+
+
+// The following define should have no effect.
+`define __FILE__ "FOO"
+
+// The following undef should have no effect.
+`undef __FILE__
+
+// NOTE: Comparison against expected value are destined to fail in testcase.
diff --git a/sv-parser-pp/testcases/expected/macro_LINE.sv b/sv-parser-pp/testcases/expected/macro_LINE.sv
@@ -0,0 +1,21 @@
+// __LINE__ = `__LINE__
+
+// This block SHOULD be emitted from the preprocessor.
+
+
+// Emitted instead.
+
+
+// The following define should have no effect.
+`define __LINE__ -2
+
+// The following undef should have no effect.
+`undef __LINE__
+
+module M;
+  initial
+    if (26 == 28)      // Should be "26 == 28".
+       $display("PASS");
+    else if (28 == 28) // Should be "28 == 28".
+       $display("FAIL");
+endmodule