Fixes bug in vhdl drive procedure

README.md

@@ -22,6 +22,12 @@ Verb is available as 3 separate components: a library for software drivers, a li
 
 Any of the components may have one or more implementations; install the component in the programming language or HDL you prefer. See [Installing](https://cdotrus.github.io/verb/starting/installing.html) for more details and available implementations.
 
+If you are using Linux or macOS, you can install all the components (using `pip`, `orbit`, and `cargo`):
+```
+curl --proto '=https' --tlsv1.2 -sSf https://github.com/cdotrus/verb/trunk/install.sh | bash -s --
+
+```
+
 ## Details
 
 Verb defines a collection of low-level functions, also known as _drivers_, that allow a user to communicate between software models and hardware designs for simulation. The main form of communication Verb uses to pass data between hardware and software is _file I/O_. This method was chosen due to its simplicity and wide support in existing HDLs. Drivers are implemented in both the software programming languages and the HDLs to faciliate the interaction between the design and the model.

install.sh

@@ -0,0 +1,9 @@
+#!/usr/bin/env bash
+
+set -e
+
+URL="https://github.com/cdotrus/verb"
+
+pip install git+$URL.git@t"runk#egg=verb&subdirectory=src/lib/python"
+orbit install verb --url $URL/archive/refs/heads/trunk.zip
+cargo install --git $URL

justfile

@@ -9,24 +9,10 @@ set windows-shell := ["powershell.exe", "-NoLogo", "-Command"]
 _default:
 	just --list
 
-VERSION := "0.1.0"
-
 # A full end-to-end test from the /examples directory
 test MOD *FLAGS:
     cd examples/{{MOD}}; orbit test --target gverb -- {{FLAGS}}
 
-pure:
-    cd examples/add; mkdir -p target/gsim
-    cd examples/add; verb model -C target/gsim --dut "$(orbit get add --json)" --tb "$(orbit get add_tb --json)" --coverage "coverage.txt" add_tb.py
-    cd examples/add; orbit t --target gsim --dut add --dirty
-    cd examples/add; verb check ./target/gsim/events.log --coverage ./target/gsim/coverage.txt --stats
-
-pure2:
-    cd examples/bcd; mkdir -p target/gsim
-    cd examples/bcd; verb model -C target/gsim --dut "$(orbit get bcd_enc --json)" --tb "$(orbit get bcd_enc_tb --json)" --coverage "coverage.txt" bcd_enc_tb.py
-    cd examples/bcd; orbit t --target gsim --dirty
-    cd examples/bcd; verb check ./target/gsim/events.log --coverage ./target/gsim/coverage.txt --stats
-
 # Test the software library
 test-sw-lib:
     python -m unittest src/lib/python/tests/*.py
@@ -41,30 +27,61 @@ test-sw-bin:
 
 # Perform an installation of the latest libraries using stable versions
 user-install:
-    just version-ok
+    just version-ok 0.1.0
     just agglo-vhdl
     pip install git+"https://github.com/cdotrus/verb.git@trunk#egg=verb"
     orbit install verb --url "https://github.com/cdotrus/verb/archive/refs/heads/trunk.zip"
     cargo install --git "https://github.com/cdotrus/verb.git"
 
 # Perform an installation of the latest libraries using development versions
 dev-install:
-    just version-ok
+    just version-ok 0.1.0
     just agglo-vhdl
     pip install -e src/lib/python --force
     orbit install --path src/lib/vhdl --force
     cargo install --path src/bin/verb --force
 
 dev-hw-install:
-    just version-ok
+    just version-ok 0.1.0
     just agglo-vhdl
     orbit install --path src/lib/vhdl --force
 
 # Checks to make sure all locations where a version is specified has the correct
 # version
-version-ok:
+version-ok VERSION:
     python scripts/version-ok.py {{VERSION}}
 
 # Updates the agglomerated VHDL package
 agglo-vhdl:
-    python scripts/agglomerate.py
+    python scripts/agglomerate.py
+
+# Run a simulation for "add" with Orbit and Verb running independent commands
+ovg-add:
+    cd examples/add; mkdir -p target/gsim
+    cd examples/add; verb model -C target/gsim --dut "$(orbit get add --json)" --tb "$(orbit get add_tb --json)" --coverage "coverage.txt" add_tb.py
+    cd examples/add; orbit t --target gsim --dut add --dirty
+    cd examples/add; verb check ./target/gsim/events.log --coverage ./target/gsim/coverage.txt --stats
+
+# Run a simulation for "bcd" with Orbit and Verb running independent commands
+ovg-bcd:
+    cd examples/bcd; mkdir -p target/gsim
+    cd examples/bcd; verb model -C target/gsim --dut "$(orbit get bcd_enc --json)" --tb "$(orbit get bcd_enc_tb --json)" --coverage "coverage.txt" bcd_enc_tb.py
+    cd examples/bcd; orbit t --target gsim --dirty
+    cd examples/bcd; verb check ./target/gsim/events.log --coverage ./target/msim/coverage.txt --stats
+
+
+# Download the latest relevant profile for Hyperspace Labs
+config:
+    git clone https://github.com/hyperspace-labs/orbit-profile.git "$(orbit env ORBIT_HOME)/profiles/hyperspace-labs"
+    pip install -r "$(orbit env ORBIT_HOME)/profiles/hyperspace-labs/requirements.txt"
+    orbit config --append include="profiles/hyperspace-labs/config.toml"
+    curl https://sh.rustup.rs -sSf | sh -s -- -y
+    install.sh
+
+# Start a docker container
+harbor:
+    docker run -it -w $PWD --mount type=bind,src=$PWD,dst=$PWD --name fpga cdotrus/melodic-marimba:latest /bin/bash
+
+# Remove the existing docker container
+sail:
+    docker container rm fpga

src/lib/vhdl/src/test.vhd

@@ -377,14 +377,16 @@ package body test is
   end procedure;
 
   procedure drive(variable row: inout line; signal x: out logics) is
-    variable word: str(x'range);
-    variable temp: logics(x'range);
+    variable word: str(1 to x'length);
+    variable temp: logics(x'range) := (others => '0');
     variable delim: char;
+    variable j: psize := 1;
   begin
     if row'length > 0 then
       read(row, word);
       for i in x'range loop
-        temp(i) := to_logic(word(i));
+        temp(i) := to_logic(word(j));
+        j := j + 1;
       end loop;
       x <= temp;
       -- ignore the delimiter
@@ -394,13 +396,15 @@ package body test is
   end procedure;
 
   procedure load(variable row: inout line; variable x: out logics) is
-    variable word: str(x'range);
+    variable word: str(1 to x'length);
     variable delim: char;
+    variable j: psize := 1;
   begin
     if row'length > 0 then
       read(row, word);
       for i in x'range loop
-        x(i) := to_logic(word(i));
+        x(i) := to_logic(word(j));
+        j := j + 1;
       end loop;
       -- ignore the delimiter
       read(row, delim);

src/lib/vhdl/src/tutils.vhd

@@ -128,14 +128,16 @@ package body tutils is
   end procedure;
 
   procedure drive(variable row: inout line; signal x: out logics) is
-    variable word: str(x'range);
-    variable temp: logics(x'range);
+    variable word: str(1 to x'length);
+    variable temp: logics(x'range) := (others => '0');
     variable delim: char;
+    variable j: psize := 1;
   begin
     if row'length > 0 then
       read(row, word);
       for i in x'range loop
-        temp(i) := to_logic(word(i));
+        temp(i) := to_logic(word(j));
+        j := j + 1;
       end loop;
       x <= temp;
       -- ignore the delimiter
@@ -145,13 +147,15 @@ package body tutils is
   end procedure;
 
   procedure load(variable row: inout line; variable x: out logics) is
-    variable word: str(x'range);
+    variable word: str(1 to x'length);
     variable delim: char;
+    variable j: psize := 1;
   begin
     if row'length > 0 then
       read(row, word);
       for i in x'range loop
-        x(i) := to_logic(word(i));
+        x(i) := to_logic(word(j));
+        j := j + 1;
       end loop;
       -- ignore the delimiter
       read(row, delim);