Adds stability task for sv package

examples/sv/bcd/bcd_enc.sv

@@ -42,7 +42,6 @@ module bcd_enc #(
 
     // simple pass through
     assign ovfl = ovfl_r;
-    assign bcd = dabble_r[LEN +: $bits(bcd)];
 
     // determine next state and output signals
     always_comb begin
@@ -54,6 +53,8 @@ module bcd_enc #(
         dabble_d = dabble_r;
         done = '0;
 
+        bcd = dabble_r[LEN +: $bits(bcd)];
+
         case(state_r)
             S_LOAD: begin
                 dabble_d = '0;
@@ -93,6 +94,8 @@ module bcd_enc #(
             end
             S_WAIT: begin
                 done = 1'b1;
+                // uncomment this line to see stability issues
+                // bcd = '0;
                 state_d = S_LOAD;
             end
             default: begin

examples/sv/bcd/bcd_enc_tb.sv

@@ -93,6 +93,15 @@ module bcd_enc_tb #(
         complete(events, halt);
     end
 
+    // parallel captures of simulation
+    string s_bcd;
+    always @(negedge clk) $sformat(s_bcd, "%b", bfm.bcd);
+    always stabilize(events, clk, s_bcd, bfm.done, 1'b1, "done's dependency bcd");
+
+    string s_ovfl;
+    always @(negedge clk) $sformat(s_ovfl, "%b", bfm.ovfl);
+    always stabilize(events, clk, s_ovfl, bfm.done, 1'b1, "done's dependency ovfl");
+
     // This task is automatically @generated by Verb.
     // It is not intended for manual editing.
     task automatic send(int i);

src/lib/hdl/src/godan.sv

@@ -130,6 +130,36 @@ package godan;
         end
     endtask;
 
+    typedef logic[127:0] logics;
+
+    // Checks the logic `data` does not change value when its indicator `flag` is in the active state `active`.
+    task stabilize(inout int fd, ref logic clk, ref string data, ref logic flag, input logic active, input string subject);
+        automatic logic is_okay = 1'b1;
+        automatic logic is_checked = 1'b0;
+        automatic string prev_data = "";
+        automatic int num_cycles = 0;
+        automatic string num_cycles_fmt = "";
+
+        @(posedge clk);
+
+        prev_data = data;
+        while(flag == active) begin
+            is_checked = 1'b1;
+            if(prev_data != data) begin
+                is_okay = 1'b0;
+                // capture
+                $sformat(num_cycles_fmt, "%-d", num_cycles);
+                capture(fd, ERROR, "STABILIZE", subject, {"loses stability of ", prev_data, " by changing to ", data, " after ", num_cycles_fmt, " cycle(s)"});
+            end
+            @(posedge clk);
+            num_cycles = num_cycles + 1;
+        end
+        if(is_checked == 1'b1 && is_okay == 1'b1) begin
+            $sformat(num_cycles_fmt, "%-d", num_cycles);
+            capture(fd, INFO, "STABILIZE", subject, {"keeps stability at ", prev_data, " for ", num_cycles_fmt, " cycle(s)"});
+        end
+    endtask
+
     // Captures an event during simulation and writes the outcome to the file `fd`.
     // The time when the task is called is recorded in the timestamp.
     task capture(inout int fd, input tone level, input string topic, input string subject, input string predicate = "");