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MIPS pipeline implementation in Verilog using Xilinx ISE.

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_xmsgs
_xmsgs
 
 
iseconfig
iseconfig
 
 
isim
isim
 
 
readme_images
readme_images
 
 
ADDER.v
ADDER.v
 
 
ADDER_tb.v
ADDER_tb.v
 
 
ADDER_tb_isim_beh.exe
ADDER_tb_isim_beh.exe
 
 
ALU.v
ALU.v
 
 
ALU_CONTROL.v
ALU_CONTROL.v
 
 
ALU_CONTROL_tb.v
ALU_CONTROL_tb.v
 
 
ALU_CONTROL_tb_isim_beh.exe
ALU_CONTROL_tb_isim_beh.exe
 
 
ALU_CONTROL_tb_stx_beh.prj
ALU_CONTROL_tb_stx_beh.prj
 
 
ALU_MUX.v
ALU_MUX.v
 
 
ALU_MUX_tb.v
ALU_MUX_tb.v
 
 
ALU_MUX_tb_isim_beh.exe
ALU_MUX_tb_isim_beh.exe
 
 
ALU_stx_beh.prj
ALU_stx_beh.prj
 
 
ALU_tb.v
ALU_tb.v
 
 
ALU_tb_isim_beh.exe
ALU_tb_isim_beh.exe
 
 
AND_Gate.v
AND_Gate.v
 
 
AND_Gate_tb.v
AND_Gate_tb.v
 
 
AND_Gate_tb_isim_beh.exe
AND_Gate_tb_isim_beh.exe
 
 
BOTTOM_MUX.v
BOTTOM_MUX.v
 
 
BOTTOM_MUX_tb.v
BOTTOM_MUX_tb.v
 
 
BOTTOM_MUX_tb_isim_beh.exe
BOTTOM_MUX_tb_isim_beh.exe
 
 
CONTROL.v
CONTROL.v
 
 
CONTROL_tb.v
CONTROL_tb.v
 
 
CONTROL_tb_isim_beh.exe
CONTROL_tb_isim_beh.exe
 
 
D_MEM.v
D_MEM.v
 
 
D_MEM_tb.v
D_MEM_tb.v
 
 
D_MEM_tb_isim_beh.exe
D_MEM_tb_isim_beh.exe
 
 
EX_MEM.v
EX_MEM.v
 
 
EX_MEM_isim_beh.exe
EX_MEM_isim_beh.exe
 
 
EX_MEM_stx_beh.prj
EX_MEM_stx_beh.prj
 
 
EX_MEM_tb.v
EX_MEM_tb.v
 
 
EX_MEM_tb_isim_beh.exe
EX_MEM_tb_isim_beh.exe
 
 
EX_MEM_tb_stx_beh.prj
EX_MEM_tb_stx_beh.prj
 
 
FETCH_isim_beh.exe
FETCH_isim_beh.exe
 
 
FETCH_isim_beh1.wdb
FETCH_isim_beh1.wdb
 
 
FETCH_summary.html
FETCH_summary.html
 
 
FETCH_tb_isim_beh.exe
FETCH_tb_isim_beh.exe
 
 
FETCH_tb_stx_beh.prj
FETCH_tb_stx_beh.prj
 
 
FORWARDING_UNIT.v
FORWARDING_UNIT.v
 
 
ID_EX.v
ID_EX.v
 
 
ID_EX_isim_beh.exe
ID_EX_isim_beh.exe
 
 
ID_EX_isim_beh1.wdb
ID_EX_isim_beh1.wdb
 
 
ID_EX_tb.v
ID_EX_tb.v
 
 
ID_EX_tb_isim_beh.exe
ID_EX_tb_isim_beh.exe
 
 
IF_ID.v
IF_ID.v
 
 
IF_ID_beh.prj
IF_ID_beh.prj
 
 
IF_ID_stx_beh.prj
IF_ID_stx_beh.prj
 
 
IF_ID_tb.v
IF_ID_tb.v
 
 
IF_ID_tb_isim_beh.exe
IF_ID_tb_isim_beh.exe
 
 
IF_ID_tb_stx_beh.prj
IF_ID_tb_stx_beh.prj
 
 
INCR.v
INCR.v
 
 
INCR_isim_beh.exe
INCR_isim_beh.exe
 
 
INCR_tb.v
INCR_tb.v
 
 
INCR_tb_isim_beh.exe
INCR_tb_isim_beh.exe
 
 
INCR_tb_stx_beh.prj
INCR_tb_stx_beh.prj
 
 
INSTR_MEM.v
INSTR_MEM.v
 
 
INSTR_MEM_isim_beh.exe
INSTR_MEM_isim_beh.exe
 
 
INSTR_MEM_isim_beh1.wdb
INSTR_MEM_isim_beh1.wdb
 
 
INSTR_MEM_tb.v
INSTR_MEM_tb.v
 
 
INSTR_MEM_tb_isim_beh.exe
INSTR_MEM_tb_isim_beh.exe
 
 
INSTR_MEM_tb_isim_beh1.wdb
INSTR_MEM_tb_isim_beh1.wdb
 
 
INSTR_MEM_tb_stx_beh.prj
INSTR_MEM_tb_stx_beh.prj
 
 
I_DECODE.v
I_DECODE.v
 
 
I_DECODE_tb.v
I_DECODE_tb.v
 
 
I_DECODE_tb_isim_beh.exe
I_DECODE_tb_isim_beh.exe
 
 
I_EXECUTE.v
I_EXECUTE.v
 
 
I_EXECUTE_beh.prj
I_EXECUTE_beh.prj
 
 
I_FETCH.v
I_FETCH.v
 
 
I_FETCH_tb.v
I_FETCH_tb.v
 
 
LICENSE
LICENSE
 
 
MEM.v
MEM.v
 
 
MEM_WB.v
MEM_WB.v
 
 
MEM_WB_tb.v
MEM_WB_tb.v
 
 
MEM_WB_tb_beh.prj
MEM_WB_tb_beh.prj
 
 
MEM_WB_tb_isim_beh.exe
MEM_WB_tb_isim_beh.exe
 
 
MEM_WB_tb_isim_beh.wdb
MEM_WB_tb_isim_beh.wdb
 
 
MEM_tb.v
MEM_tb.v
 
 
MEM_tb_isim_beh.exe
MEM_tb_isim_beh.exe
 
 
MIPS.gise
MIPS.gise
 
 
MIPS.xise
MIPS.xise
 
 
MUX.v
MUX.v
 
 
MUX_tb.v
MUX_tb.v
 
 
MUX_tb_isim_beh.exe
MUX_tb_isim_beh.exe
 
 
MUX_tb_stx_beh.prj
MUX_tb_stx_beh.prj
 
 
PC.v
PC.v
 
 
PC_isim_beh.exe
PC_isim_beh.exe
 
 
PC_stx_beh.prj
PC_stx_beh.prj
 
 
PC_summary.html
PC_summary.html
 
 
PC_tb.v
PC_tb.v
 
 
PC_tb_isim_beh.exe
PC_tb_isim_beh.exe
 
 
PC_tb_stx_beh.prj
PC_tb_stx_beh.prj
 
 
PIPELINE.v
PIPELINE.v
 
 
PIPELINE_isim_beh.exe
PIPELINE_isim_beh.exe
 
 
PIPELINE_stx_beh.prj
PIPELINE_stx_beh.prj
 
 
PIPELINE_summary.html
PIPELINE_summary.html
 
 
PIPELINE_tb.v
PIPELINE_tb.v
 
 
PIPELINE_tb_beh.prj
PIPELINE_tb_beh.prj
 
 

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MIPS

MIPS pipeline implementation in Verilog using Xilinx ISE. Instructions and data were statically initialized for testing purposes.

MIPS Pipeline

Pipeline

IF Stage

IF Stage

ID Stage

ID Stage

EX Stage

EX Stage

MEM Stage

MEM Stage

WB Stage

WB Stage

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MIPS pipeline implementation in Verilog using Xilinx ISE.

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