4bitCounterParLoad

A 4bit Binary Counter with Parallel Load including a clock divider, a BCD decoder and a 7 segment display.

Information

This is a VHDL project for DSD-I1* a Cyclone IV FPGA made in Quartus 18.1 and is based in the example of pjbal.

Diagram:

Behavioral VHDL code: nbit_syncCount_parLoad.vhd
Testbench VHDL code: nbit_syncCount_parLoad_tb.vhd

Modelsim:

FPGA:

*Note: DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education DOI:10.1109/DSD.2019.00032

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
db		db
incremental_db		incremental_db
output_files		output_files
4bitCounterParLoad.jpg		4bitCounterParLoad.jpg
4bitCounterParLoad_fpga.jpg		4bitCounterParLoad_fpga.jpg
4bitCounterParLoad_modelsim.jpg		4bitCounterParLoad_modelsim.jpg
4bitCounter_ParLoad.qpf		4bitCounter_ParLoad.qpf
4bitCounter_ParLoad.qsf		4bitCounter_ParLoad.qsf
4bitCounter_ParLoad_description.txt		4bitCounter_ParLoad_description.txt
HalfAdder_VHDL.vhd		HalfAdder_VHDL.vhd
README.md		README.md
TwoInputAND_VHDL.vhd		TwoInputAND_VHDL.vhd
TwoInputMultiplexor_VHDL.vhd		TwoInputMultiplexor_VHDL.vhd
TwoInputXOR_VHDL.vhd		TwoInputXOR_VHDL.vhd
bcd7seg.vhd		bcd7seg.vhd
bcd7seg.vhd.bak		bcd7seg.vhd.bak
clock_div.vhd		clock_div.vhd
clock_div.vhd.bak		clock_div.vhd.bak
dFlipFlop.vhd		dFlipFlop.vhd
dFlipFlop.vhd.bak		dFlipFlop.vhd.bak
nbitReg.vhd		nbitReg.vhd
nbitReg.vhd.bak		nbitReg.vhd.bak
nbitTwoInputMux_VHDL.vhd		nbitTwoInputMux_VHDL.vhd
nbitTwoInputMux_VHDL.vhd.bak		nbitTwoInputMux_VHDL.vhd.bak
nbit_incrementor.vhd		nbit_incrementor.vhd
nbit_incrementor.vhd.bak		nbit_incrementor.vhd.bak
nbit_syncCount_parLoad.vhd		nbit_syncCount_parLoad.vhd
nbit_syncCount_parLoad.vhd.bak		nbit_syncCount_parLoad.vhd.bak