fix: Hitag S logtrace time #2522
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You are welcome to add an entry to the CHANGELOG.md as well |
armsrc/hitagS.c
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| AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | ||
| AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | ||
| AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; | ||
| AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; |
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there is a bug mentioned in the errata of the arm chip, use previous declaration.
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I didn't find any Timer Counter info in the errata section. If you are referring to the reset, the three timer counters are reset together using AT91C_BASE_TCB->TCB_BCR = 1
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No.
And then I will close this PR.
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Yes, that would be the ones.
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Great! Then the reset is already handled together using the SYNC signal (AT91C_BASE_TCB->TCB_BCR = 1) which generates a software trigger for each channel simultaneously. I think it's ready to be merged.
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No,
Revert back the = AT91C_TC_CLKEN | AT91C_TC_SWTRG parts.
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But why? The reset is properly handled by the SYNC signal. Is the redundant code for bug-proofing in case someone copy/paste it elsewhere, or just to maintain consistent code style?
Anyway, I will revert it back. Please reopen this PR
armsrc/hitagS.c
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| AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | ||
| AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; | ||
| AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; | ||
| AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; |
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same as previous comment
douniwan5788
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