Proper cache management.

[iabdalkader]

I'm using OpenAMP on a dual core M7/M4 microcontroller, and I'm trying to enable cache management with VIRTIO_USE_DCACHE. I implemented metal_machine_cache_flush and metal_machine_cache_invalidate but then I realized that those functions are called with unaligned addresses, and sizes that are not a multiple of the cache line size. I don't see any configuration option to set the cache line size, so I'm wondering if those functions were meant do more complex cache management than simply just flush/invalidate whatever address/size that gets passed to them ?
Another question related to caching, if other OpenAMP structures are allocated dynamically in another memory region, which is cached, do those structs need cache management ? For example rpmsg_virtio_device, rpmsg_virtio_shm_pool and so on ? Thanks!

[arnopo]

I'm using OpenAMP on a dual core M7/M4 microcontroller, and I'm trying to enable cache management with VIRTIO_USE_DCACHE. I implemented metal_machine_cache_flush and metal_machine_cache_invalidate but then I realized that those functions are called with unaligned addresses, and sizes that are not a multiple of the cache line size. I don't see any configuration option to set the cache line size, so I'm wondering if those functions were meant do more complex cache management than simply just flush/invalidate whatever address/size that gets passed to them ?

It depends on your need, these functions can be redirect to some OS functions as done for instance for NuttX or Zephyr or to implement your own cache management. you have to align on cache lines in these functions.

Another question related to caching, if other OpenAMP structures are allocated dynamically in another memory region, which is cached, do those structs need cache management ? For example rpmsg_virtio_device, rpmsg_virtio_shm_pool and so on ? Thanks!

You should only need to manage the cache for memories that are shared between the 2 cores. Except bug, code is already present to manage the structures in shared memory. The structure you mention are local structures.

[iabdalkader]

Hi @arnopo

these functions can be redirect to some OS functions as done for instance for NuttX or Zephyr or to implement your own cache management. you have to align on cache lines in these functions.

There's no OS it's just baremetal, and the CMSIS functions do align the address and round the size up to a multiple of cache line size, but that can have side effects and corrupt other data. I guess more complex cache management is indeed required, but for now I'll just disable caching for the whole region.

You should only need to manage the cache for memories that are shared between the 2 cores

Understood, thank you for the reply!