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Simple tri_state buffer bus

This small repository contains an educational example of a tri_state buffer bus in Verilog. The bus can be read and written by 3 components (but only one at a time), depending on which tri-state buffer is enabled. Waveform and the structure of the module can be seen in the photo.

To run the code:

$ make

Dependencies: iverilog and gtkwave

Architecture

Waveform

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Educational example of a tri-state buffer bus

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