usb: host: jz4780-ehci: Remove duplicate defines from jz4780-cgu.c

MIPS · Jun 22, 2015 · efdb012 · efdb012
1 parent 4b75fea
commit efdb012
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 89 deletions.
diff --git a/arch/mips/include/asm/mach-jz4740/jz4780-cgu.h b/arch/mips/include/asm/mach-jz4740/jz4780-cgu.h
@@ -115,6 +115,8 @@
 
 /* Bits within the UTMI Bus register */
 #define UTMIBUS_WIDTH		BIT(6)
+/* bits within the SRBC register */
+#define SRBC_UHC_SR		BIT(14)
 
 /* bits within the SRBC register */
 #define SRBC_UHC_SR		BIT(14)

diff --git a/drivers/clk/jz47xx/jz4780-cgu.c b/drivers/clk/jz47xx/jz4780-cgu.c
@@ -27,95 +27,6 @@
 #include "jz47xx-cgu.h"
 #include <asm/mach-jz4740/jz4780-cgu.h>
 
-/* CGU register offsets */
-#define CGU_REG_CLOCKCONTROL	0x00
-#define CGU_REG_PLLCONTROL	0x0c
-#define CGU_REG_APLL		0x10
-#define CGU_REG_MPLL		0x14
-#define CGU_REG_EPLL		0x18
-#define CGU_REG_VPLL		0x1c
-#define CGU_REG_OPCR		0x24
-#define CGU_REG_DDRCDR		0x2c
-#define CGU_REG_VPUCDR		0x30
-#define CGU_REG_USBPCR		0x3c
-#define CGU_REG_USBRDT		0x40
-#define CGU_REG_USBVBFIL	0x44
-#define CGU_REG_USBPCR1		0x48
-#define CGU_REG_LP0CDR		0x54
-#define CGU_REG_I2SCDR		0x60
-#define CGU_REG_LP1CDR		0x64
-#define CGU_REG_MSC0CDR		0x68
-#define CGU_REG_UHCCDR		0x6c
-#define CGU_REG_SSICDR		0x74
-#define CGU_REG_CIMCDR		0x7c
-#define CGU_REG_PCMCDR		0x84
-#define CGU_REG_GPUCDR		0x88
-#define CGU_REG_HDMICDR		0x8c
-#define CGU_REG_MSC1CDR		0xa4
-#define CGU_REG_MSC2CDR		0xa8
-#define CGU_REG_BCHCDR		0xac
-#define CGU_REG_SRBC		0xc4
-#define CGU_REG_CLOCKSTATUS	0xd4
-
-/* bits within a PLL control register */
-#define PLLCTL_M_SHIFT		19
-#define PLLCTL_M_MASK		(0x1fff << PLLCTL_M_SHIFT)
-#define PLLCTL_N_SHIFT		13
-#define PLLCTL_N_MASK		(0x3f << PLLCTL_N_SHIFT)
-#define PLLCTL_OD_SHIFT		9
-#define PLLCTL_OD_MASK		(0xf << PLLCTL_OD_SHIFT)
-#define PLLCTL_ON		(1 << 4)
-#define PLLCTL_BYPASS		(1 << 1)
-#define PLLCTL_ENABLE		(1 << 0)
-
-/* bits within the OPCR register */
-#define OPCR_SPENDN0		(1 << 7)
-#define OPCR_SPENDN1		(1 << 6)
-
-/* bits within the USBPCR register */
-#define USBPCR_USB_MODE		BIT(31)
-#define USBPCR_IDPULLUP_MASK	(0x3 << 28)
-#define USBPCR_COMMONONN	BIT(25)
-#define USBPCR_VBUSVLDEXT	BIT(24)
-#define USBPCR_VBUSVLDEXTSEL	BIT(23)
-#define USBPCR_POR		BIT(22)
-#define USBPCR_OTG_DISABLE	BIT(20)
-#define USBPCR_COMPDISTUNE_MASK	(0x7 << 17)
-#define USBPCR_OTGTUNE_MASK	(0x7 << 14)
-#define USBPCR_SQRXTUNE_MASK	(0x7 << 11)
-#define USBPCR_TXFSLSTUNE_MASK	(0xf << 7)
-#define USBPCR_TXPREEMPHTUNE	BIT(6)
-#define USBPCR_TXHSXVTUNE_MASK	(0x3 << 4)
-#define USBPCR_TXVREFTUNE_MASK	0xf
-
-/* bits within the USBPCR1 register */
-#define USBPCR1_REFCLKSEL_SHIFT	26
-#define USBPCR1_REFCLKSEL_MASK	(0x3 << USBPCR1_REFCLKSEL_SHIFT)
-#define USBPCR1_REFCLKSEL_CORE	(0x2 << USBPCR1_REFCLKSEL_SHIFT)
-#define USBPCR1_REFCLKDIV_SHIFT	24
-#define USBPCR1_REFCLKDIV_MASK	(0x3 << USBPCR1_REFCLKDIV_SHIFT)
-#define USBPCR1_REFCLKDIV_19_2	(0x3 << USBPCR1_REFCLKDIV_SHIFT)
-#define USBPCR1_REFCLKDIV_48	(0x2 << USBPCR1_REFCLKDIV_SHIFT)
-#define USBPCR1_REFCLKDIV_24	(0x1 << USBPCR1_REFCLKDIV_SHIFT)
-#define USBPCR1_REFCLKDIV_12	(0x0 << USBPCR1_REFCLKDIV_SHIFT)
-#define USBPCR1_USB_SEL		BIT(28)
-#define USBPCR1_WORD_IF0	BIT(19)
-#define USBPCR1_WORD_IF1	BIT(18)
-#define USBPCR1_DPPD1		BIT(22)
-#define USBPCR1_DMPD1		BIT(23)
-
-/* bits within the USBRDT register */
-#define USBRDT_VBFIL_LD_EN	BIT(25)
-#define USBRDT_USBRDT_MASK	0x7fffff
-
-/* bits within the USBVBFIL register */
-#define USBVBFIL_IDDIGFIL_SHIFT	16
-#define USBVBFIL_IDDIGFIL_MASK	(0xffff << USBVBFIL_IDDIGFIL_SHIFT)
-#define USBVBFIL_USBVBFIL_MASK	(0xffff)
-
-/* bits within the SRBC register */
-#define SRBC_UHC_SR		BIT(14)
-
 static struct jz47xx_cgu *cgu;
 
 static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)