Merge pull request #25 from tasmota/master

Updates from upstream master

.github/workflows/dangerjs.yml

@@ -1,18 +1,21 @@
 name: DangerJS Check
 on:
-  pull_request:
+  pull_request_target:
     types: [opened, edited, reopened, synchronize]
 
 permissions:
   pull-requests: write
-  statuses: write
+  contents: write
 
 jobs:
   pull-request-style-linter:
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v3
-
+    - name: Check out PR head
+      uses: actions/checkout@v3
+      with:
+        ref: ${{ github.event.pull_request.head.sha }}
+
     - name: DangerJS pull request linter
       uses: espressif/github-actions/danger_pr_review@master
       env:

.gitlab-ci.yml

@@ -1,10 +1,13 @@
 # Gitlab CI config
 #
 # Note: When updating, please also update test_esptool.yml GH Actions workflow file
-include:
-  - project: 'espressif/shared-ci-dangerjs'
-    ref: master
-    file: 'danger.yaml'
+stages:
+  - pre-check
+  - test
+  - report
+  - build_docs
+  - deploy_docs
+  - deploy_development_package
 
 workflow:
   rules:
@@ -13,13 +16,12 @@ workflow:
       when: never
     - if: '$CI_COMMIT_BRANCH'
 
-stages:
-  - danger
-  - test
-  - report
-  - build_docs
-  - deploy_docs
-  - deploy_development_package
+include:
+    - project: espressif/shared-ci-dangerjs
+      ref: master
+      file: danger.yaml
+run-danger-mr-linter:
+    stage: pre-check
 
 # cache the pip download directory in all jobs
 variables:
@@ -84,6 +86,7 @@ host_tests:
     - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2beta1
     - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c6
     - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2
+    - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32p4
     # some .coverage files in sub-directories are not collected on some runners, move them first
     - find . -mindepth 2 -type f -name ".coverage*" -print -exec mv --backup=numbered {} . \;
 

.pre-commit-config.yaml

@@ -3,13 +3,15 @@ repos:
     rev: 4.0.1
     hooks:
       - id: flake8
+        additional_dependencies: [flake8-import-order]
   - repo: https://github.com/psf/black
     rev: 22.3.0
     hooks:
       - id: black
   - repo: https://github.com/espressif/conventional-precommit-linter
-    rev: v1.2.0
+    rev: v1.2.1
     hooks:
       - id: conventional-precommit-linter
         stages: [commit-msg]
+default_stages: [commit]
 default_install_hook_types: [pre-commit, commit-msg]

docs/en/contributing.rst

@@ -1 +1,3 @@
+.. _contribute:
+
 .. include:: ../../CONTRIBUTING.rst

docs/en/espsecure/index.rst

@@ -50,6 +50,9 @@ HSM config file
 An HSM config file is required with the fields (``pkcs11_lib``, ``credentials``, ``slot``, ``label``, ``label_pubkey``)
 populated corresponding to the HSM used.
 
+To access an HSM token of a selected slot, you will also need to pass in the token User PIN and thus you will be prompted to type in the User PIN.
+Alternatively, you could also add a ``credentials`` field in the HSM config file to store the (plaintext) User PIN to automate the signing workflow.
+
 Below is a sample HSM config file (``hsm_config.ini``) for using `SoftHSMv2 <https://github.com/opendnssec/SoftHSMv2>`_ as an external HSM: ::
 
     # hsm_config.ini

docs/en/index.rst

@@ -51,4 +51,5 @@ More Information
    Troubleshooting <troubleshooting>
    Contribute <contributing>
    Versions <versions>
+   Resources <resources>
    About <about>

docs/en/resources.rst

@@ -0,0 +1,40 @@
+.. _resources:
+
+Resources
+=========
+
+
+Useful Links
+-------------
+
+* The `esp32.com forum <https://esp32.com/>`_ is a place to ask questions and find community resources.
+
+* Check the `Issues <https://github.com/espressif/esptool/issues>`_  section on GitHub if you find a bug or have a feature request. Please check existing `issues <https://github.com/espressif/esptool/issues>`_ before opening a new one.
+
+* Several `books <https://www.espressif.com/en/ecosystem/community-engagement/books>`_ have been written about the ESP8266 or ESP32 series of SoCs and they are listed on `Espressif <https://www.espressif.com/en/ecosystem/community-engagement/books>`__ web site.
+
+* If you're interested in contributing to esptool.py, please check the :ref:`contribute` page.
+
+* For additional {IDF_TARGET_NAME} product related information, please refer to the `documentation <https://espressif.com/en/support/download/documents>`_ section of `Espressif <https://espressif.com/en/support/download/documents>`__ web site.
+
+Webinars and Trainings
+----------------------
+
+Mastering the Basics of Espressif Chips: An In-Depth Look at Chip Flashing
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The content of this webinar is designed for developers, engineers and hobbyists interested in getting a better understanding of how to use esptool.py or other tools for the development with the ESP8266 or ESP32 series of SoCs.
+
+It offers an in-depth look at the inner mechanisms of esptool.py, including the :ref:`boot-mode` process.
+
+.. image:: https://img.youtube.com/vi/zh-Y_s4X6zs/maxresdefault.jpg
+    :alt: Mastering the Basics of Espressif Chips: An In-Depth Look at Chip Flashing
+    :target: https://www.youtube.com/watch?v=zh-Y_s4X6zs
+
+DevCon22: esptool.py: Espressif's Swiss Army Knife
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+This talk aims to show how simple, yet powerful, esptool.py is, and how to use it to tame your ESP.
+
+.. image:: https://img.youtube.com/vi/GjWGKzu3XTk/maxresdefault.jpg
+    :alt: DevCon22: esptool.py: Espressif's Swiss Army Knife
+    :target: https://www.youtube.com/watch?v=GjWGKzu3XTk

espefuse/__init__.py

@@ -14,6 +14,7 @@
 import espefuse.efuse.esp32c6 as esp32c6_efuse
 import espefuse.efuse.esp32h2 as esp32h2_efuse
 import espefuse.efuse.esp32h2beta1 as esp32h2beta1_efuse
+import espefuse.efuse.esp32p4 as esp32p4_efuse
 import espefuse.efuse.esp32s2 as esp32s2_efuse
 import espefuse.efuse.esp32s3 as esp32s3_efuse
 import espefuse.efuse.esp32s3beta2 as esp32s3beta2_efuse
@@ -49,6 +50,7 @@
     "esp32c3": DefChip("ESP32-C3", esp32c3_efuse, esptool.targets.ESP32C3ROM),
     "esp32c6": DefChip("ESP32-C6", esp32c6_efuse, esptool.targets.ESP32C6ROM),
     "esp32h2": DefChip("ESP32-H2", esp32h2_efuse, esptool.targets.ESP32H2ROM),
+    "esp32p4": DefChip("ESP32-P4", esp32p4_efuse, esptool.targets.ESP32P4ROM),
     "esp32h2beta1": DefChip(
         "ESP32-H2(beta1)", esp32h2beta1_efuse, esptool.targets.ESP32H2BETA1ROM
     ),

espefuse/efuse/esp32p4/__init__.py

@@ -0,0 +1,3 @@
+from . import operations
+from .emulate_efuse_controller import EmulateEfuseController
+from .fields import EspEfuses

espefuse/efuse/esp32p4/emulate_efuse_controller.py

@@ -0,0 +1,92 @@
+# This file describes eFuses controller for ESP32-P4 chip
+#
+# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import reedsolo
+
+from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters
+from ..emulate_efuse_controller_base import EmulateEfuseControllerBase, FatalError
+
+
+class EmulateEfuseController(EmulateEfuseControllerBase):
+    """The class for virtual efuse operation. Using for HOST_TEST."""
+
+    CHIP_NAME = "ESP32-P4"
+    mem = None
+    debug = False
+
+    def __init__(self, efuse_file=None, debug=False):
+        self.Blocks = EfuseDefineBlocks
+        self.Fields = EfuseDefineFields()
+        self.REGS = EfuseDefineRegisters
+        super(EmulateEfuseController, self).__init__(efuse_file, debug)
+        self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
+
+    """ esptool method start >>"""
+
+    def get_major_chip_version(self):
+        return 0
+
+    def get_minor_chip_version(self):
+        return 0
+
+    def get_crystal_freq(self):
+        return 40  # MHz (common for all chips)
+
+    def get_security_info(self):
+        return {
+            "flags": 0,
+            "flash_crypt_cnt": 0,
+            "key_purposes": 0,
+            "chip_id": 0,
+            "api_version": 0,
+        }
+
+    """ << esptool method end """
+
+    def handle_writing_event(self, addr, value):
+        if addr == self.REGS.EFUSE_CMD_REG:
+            if value & self.REGS.EFUSE_PGM_CMD:
+                self.copy_blocks_wr_regs_to_rd_regs(updated_block=(value >> 2) & 0xF)
+                self.clean_blocks_wr_regs()
+                self.check_rd_protection_area()
+                self.write_reg(addr, 0)
+                self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
+            elif value == self.REGS.EFUSE_READ_CMD:
+                self.write_reg(addr, 0)
+                self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
+                self.save_to_file()
+
+    def get_bitlen_of_block(self, blk, wr=False):
+        if blk.id == 0:
+            if wr:
+                return 32 * 8
+            else:
+                return 32 * blk.len
+        else:
+            if wr:
+                rs_coding = 32 * 3
+                return 32 * 8 + rs_coding
+            else:
+                return 32 * blk.len
+
+    def handle_coding_scheme(self, blk, data):
+        if blk.id != 0:
+            # CODING_SCHEME RS applied only for all blocks except BLK0.
+            coded_bytes = 12
+            data.pos = coded_bytes * 8
+            plain_data = data.readlist("32*uint:8")[::-1]
+            # takes 32 bytes
+            # apply RS encoding
+            rs = reedsolo.RSCodec(coded_bytes)
+            # 32 byte of data + 12 bytes RS
+            calc_encoded_data = list(rs.encode([x for x in plain_data]))
+            data.pos = 0
+            if calc_encoded_data != data.readlist("44*uint:8")[::-1]:
+                raise FatalError("Error in coding scheme data")
+            data = data[coded_bytes * 8 :]
+        if blk.len < 8:
+            data = data[(8 - blk.len) * 32 :]
+        return data