Skip to content

Update README.md #22

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Update README.md #22

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ If you don't want to go through the hassle of ordering parts, tools, and supplie

## Project Directory Structure
### board
This contains a [KiCad](http://kicad-pcb.org/) project with the schematic and layout of the B-series boards. The board is designed with 4/4mil track size/spacing and 0.2mm hole size. BOM lists for B1 and B2 boards are available here as well.
This contains a [KiCad](http://kicad.org/) project with the schematic and layout of the B-series boards. The board is designed with 4/4mil track size/spacing and 0.2mm hole size. BOM lists for B1 and B2 boards are available here as well.

### bootloader
FPGA boards with USB bitstream programming capability typically use an expensive USB interface chip to provide this functionality. The TinyFPGA B-series implement the USB bitstream programming capability within the FPGA itself. This directory contains the verilog code that implements this bootloader. The code is organized as an [iCEcube2](http://www.latticesemi.com/iCEcube2) project. The bootloader itself works in the same way an Arduino bootloader works. It is the first design to boot on the FPGA, if it is connected to a USB host it waits for a new bitstream to be programmed to the SPI flash, then reboots the FPGA to load the user design from flash. If the board is not connected to a USB host or if there is no programmer application running on the host then the bootloader will quickly timeout and load the user design. The bootloader does not consume any FPGA resources while the user design is loaded.
Expand Down