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soc_core:allocate correct size for ROM. #97

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soc_core:allocate correct size for ROM. #97

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8 changes: 5 additions & 3 deletions misoc/integration/soc_core.py
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Original file line number Diff line number Diff line change
Expand Up @@ -135,9 +135,11 @@ def register_mem(self, name, origin, length, interface):

def register_rom(self, interface, rom_size=0xa000):
self.add_wb_slave(self.mem_map["rom"], rom_size, interface)
assert self.cpu_reset_address < rom_size
self.add_memory_region("rom", self.cpu_reset_address,
rom_size-self.cpu_reset_address)
if not self.mem_map["rom"] == self.cpu_reset_address:
raise ValueError(
"CPU reset address 0x{:x} is not equal to the rom start addres 0x{:x}"
.format(self.cpu_reset_address,self.mem_map["rom"]))
self.add_memory_region("rom", self.mem_map["rom"],rom_size)
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I validated that this code now allows to map the rom section to a different address and that the code still works and believe all comments stated where resolved.

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@sbourdeauducq sbourdeauducq Feb 6, 2019 •
edited
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Style issues:

  • != and not not ==
  • space after comma

I believe that many targets and ARTIQ in particular have a reset address within the ROM (beginning of the ROM is the FPGA bitstream), so your change will break them.
If the reset address was always the ROM start, we would not need two parameters.


def get_memory_regions(self):
return self._memory_regions
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