Rev 6

6.0 (2018-01-29)

• Improved Ethernet support (for FPGA V2.X)
• Improved efficiency of FireWire broadcast protocol by skipping boards that are on the bus, but not used by the current configuration.
• Improved timeliness of velocity estimation by measuring time between all encoder edges (e.g., A-up to A-up, A-down to A-down, B-up to B-up, B-down to B-down) and by providing additional data to enable the higher-level software to estimate acceleration from the backward difference of the last two velocities. Increased time measurement clock from 768 kHz to 3.072 MHz for better resolution and increased range from 16 bits to 22 bits (for time between encoder edges of same type).
• Corrected PWM and single-shot behaviors on digital outputs for QLA Rev 1.4+
• Added bit to status register to indicate motor voltage fault, MV-FLT (QLA Rev 1.4+)
• Clear Watchdog Timeout (bit 23) and Feedback Current Check (bits 7-4) when enabling board power or amplifier power. In prior versions of the firmware, these bits were cleared by any write command and thus could easily be missed.