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FPGA implementation of singular value decomposition

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FPGA_SVD

FPGA implementation of singular value decomposition

This is a project for my digital electronics class.

To use, enter [# #;# #] over PUTTY. Due to resource limitations I have kept it to 2x2 matrices.

Uses Hestenes-Jacobi SVD algorithm.

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FPGA implementation of singular value decomposition

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VHDL 100.0%