HDL Gen Hub is a project of creating an E-Learning platform to teach Hardware Description Languages, specially Verilog.
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This is a group project for the Software Group Project module at the Faculty of Engineering, University of Ruhuna. The project is to create a web application that allows users to generate HDL code from Verilog Compiler.
- MongoDB
- Express
- React
- Node.js
- Tailwind CSS
- Docker
- Siriwardhana T.D.R.D. (EG/2020/4219)
- Sandarenu D.T (EG/2020/4191)
- Jayarathne G.U.T.N.C. (EG/2020/3981)
- Nethsarani D.W.D. (EG/2020/4096)
