questasim
Here are 31 public repositories matching this topic...
This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.
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Aug 26, 2024 - SystemVerilog
CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations
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Nov 28, 2023 - Python
A solution of test assignment from company
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Jan 7, 2020 - SystemVerilog
In-Memory Accelerator Controller
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Sep 13, 2024 - SystemVerilog
This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com
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Jun 25, 2021 - Verilog
Попытка написать несколько примеров кода на языке SystemVerilog.
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Mar 11, 2021 - SystemVerilog
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
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May 26, 2024 - Verilog
SublimeLinter plugin for linting VHDL with Modelsim vcom
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Dec 21, 2017 - Python
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
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May 28, 2024 - Verilog
Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate th…
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May 18, 2021 - Verilog
Latest addition to REPO : Folder with vending machine design and TB including code coverage report
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May 21, 2023 - HTML
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
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Jun 26, 2024 - Verilog
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
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Aug 4, 2024 - Verilog
⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.
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Nov 9, 2018 - Python
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
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Dec 21, 2017 - Python
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