In-Memory Accelerator Controller
-
Updated
Sep 13, 2024 - SystemVerilog
In-Memory Accelerator Controller
Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate th…
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com
This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.
CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations
Попытка написать несколько примеров кода на языке SystemVerilog.
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
A solution of test assignment from company
Latest addition to REPO : Folder with vending machine design and TB including code coverage report
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
SublimeLinter plugin for linting VHDL with Modelsim vcom
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
Add a description, image, and links to the questasim topic page so that developers can more easily learn about it.
To associate your repository with the questasim topic, visit your repo's landing page and select "manage topics."