Verilog implementation of 16-bit RISC Processor with 4-stage pipeline
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Updated
May 4, 2018 - Verilog
Verilog implementation of 16-bit RISC Processor with 4-stage pipeline
Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme
Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor
This is an implementation of a simple CPU in Logisim and Verilog.
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.
Single-cycle and multi-cycle implementation of a subset of MIPS instruction set
Verilog CPU Design Project, ELEC 374 - Digital Systems Engineering
Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022
This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.
In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
Sample Verilog codes for digital circuits
This repository contains files regarding my CPU designs
These files make up my home made processor in Verilog. I simulated my processor on an FPGA to create an arcade style duck hunt game!
phoeniX RISC-V Processor
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